1# Copyright (c) 2021 Microchip Technology Inc.
2# SPDX-License-Identifier: Apache-2.0
3
4description: Microchip XEC eSPI Virtual Wire routing
5
6compatible: "microchip,xec-espi-vw-routing"
7
8include: [base.yaml]
9
10child-binding:
11  description: |
12    Child node containing the routing of an eSPI virtual wire to the SoC
13    VW registers and ECIA GIRQ registers.
14  properties:
15    vw-reg:
16      type: array
17      required: true
18      description: vw signal's register index and vw bitmask.
19
20    vw-girq:
21      type: array
22      description: |
23        Routing of MSVW source to aggregated GIRQs
24
25        For example, OOB_RST_WARN is source 2 of MSVW01 routed
26        to GIRQ24 b[5]. vw-girq = <24 5>;
27
28    reset-state:
29      type: string
30      description: |
31        Optional default virtual wire state on reset (0 or 1).
32        If the property is not present hardware default is used.
33      enum:
34      - "HW_DFLT"
35      - "0"
36      - "1"
37
38    reset-source:
39      type: string
40      description: |
41        Optional reset source in addition to chip reset.
42        0 is ESPI_RESET, 1 is RESET_SYS, 2 is RESET_SIO,
43        and 3 is ESPI Platform Reset. If this property is not
44        present the hardware default is used. Note: reset source
45        affects all four virtual wires in the VW group.
46      enum:
47      - "HW_DFLT"
48      - "ESPI_RESET"
49      - "RESET_SYS"
50      - "RESET_SIO"
51      - "PLTRST"
52