1description: Atmel SAM0 DMA controller
2
3compatible: "atmel,sam0-dmac"
4
5include: dma-controller.yaml
6
7properties:
8  reg:
9    required: true
10
11  interrupts:
12    required: true
13
14  "#dma-cells":
15    const: 2
16
17# #dma-cells : Must be <2>.
18# The 1st cell specifies the DMAC channel to be used for the data transfer.
19#   This channel should be unique between all peripherals that are using the
20#   DMAC instance.
21# The 2nd cell defines the peripheral trigger which is the source of the transfer.
22#   For details on trigger selection and trigger modes, refer to
23#   "Transfer Triggers and Actions".
24#   See the SoC's reference manual for all the supported request sources.
25#
26# Example of devicetree dma channel configuration:
27#
28# &sercom3 {
29#     /* Configure DMA channels for async operation */
30#     dmas = <&dmac 10 7>, <&dmac 11 8>;
31#     dma-names = "rx", "tx";
32# };
33#
34# In above fragment 10 and 11 represents the different channels used to
35# transfer data between peripheral and ram. The numbers 7/8 are, for instance,
36# uart_rx/tx peripheral trigger for sercom3.
37dma-cells:
38  - channel
39  - trigsrc
40