1/* 2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or 3 * an affiliate of Cypress Semiconductor Corporation 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu@0 { 16 device_type = "cpu"; 17 compatible = "arm,cortex-m0+"; 18 reg = <0>; 19 }; 20 cpu@1 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-m4f"; 23 reg = <1>; 24 }; 25 }; 26 27 flash-controller@40240000 { 28 compatible = "infineon,cat1-flash-controller"; 29 reg = < 0x40240000 0x10000 >; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 33 flash0: flash@10000000 { 34 compatible = "soc-nv-flash"; 35 reg = <0x10000000 0x80000>; 36 write-block-size = <512>; 37 erase-block-size = <512>; 38 }; 39 flash1: flash@14000000 { 40 compatible = "soc-nv-flash"; 41 reg = <0x14000000 0x8000>; 42 write-block-size = <512>; 43 erase-block-size = <512>; 44 }; 45 }; 46 47 sram0: memory@8000000 { 48 compatible = "mmio-sram"; 49 reg = <0x8000000 0x40000>; 50 }; 51 52 soc { 53 pinctrl: pinctrl@40300000 { 54 compatible = "infineon,cat1-pinctrl"; 55 reg = <0x40300000 0x20000>; 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 hsiom: hsiom@40300000 { 60 compatible = "infineon,cat1-hsiom"; 61 reg = <0x40300000 0x4000>; 62 interrupts = <15 6>, <16 6>; 63 status = "disabled"; 64 }; 65 66 gpio_prt0: gpio@40310000 { 67 compatible = "infineon,cat1-gpio"; 68 reg = <0x40310000 0x80>; 69 interrupts = <0 6>; 70 gpio-controller; 71 ngpios = <6>; 72 status = "disabled"; 73 #gpio-cells = <2>; 74 }; 75 gpio_prt2: gpio@40310100 { 76 compatible = "infineon,cat1-gpio"; 77 reg = <0x40310100 0x80>; 78 interrupts = <2 6>; 79 gpio-controller; 80 ngpios = <8>; 81 status = "disabled"; 82 #gpio-cells = <2>; 83 }; 84 gpio_prt3: gpio@40310180 { 85 compatible = "infineon,cat1-gpio"; 86 reg = <0x40310180 0x80>; 87 interrupts = <3 6>; 88 gpio-controller; 89 ngpios = <2>; 90 status = "disabled"; 91 #gpio-cells = <2>; 92 }; 93 gpio_prt5: gpio@40310280 { 94 compatible = "infineon,cat1-gpio"; 95 reg = <0x40310280 0x80>; 96 interrupts = <5 6>; 97 gpio-controller; 98 ngpios = <4>; 99 status = "disabled"; 100 #gpio-cells = <2>; 101 }; 102 gpio_prt6: gpio@40310300 { 103 compatible = "infineon,cat1-gpio"; 104 reg = <0x40310300 0x80>; 105 interrupts = <6 6>; 106 gpio-controller; 107 ngpios = <8>; 108 status = "disabled"; 109 #gpio-cells = <2>; 110 }; 111 gpio_prt7: gpio@40310380 { 112 compatible = "infineon,cat1-gpio"; 113 reg = <0x40310380 0x80>; 114 interrupts = <7 6>; 115 gpio-controller; 116 ngpios = <8>; 117 status = "disabled"; 118 #gpio-cells = <2>; 119 }; 120 gpio_prt8: gpio@40310400 { 121 compatible = "infineon,cat1-gpio"; 122 reg = <0x40310400 0x80>; 123 interrupts = <8 6>; 124 gpio-controller; 125 ngpios = <4>; 126 status = "disabled"; 127 #gpio-cells = <2>; 128 }; 129 gpio_prt9: gpio@40310480 { 130 compatible = "infineon,cat1-gpio"; 131 reg = <0x40310480 0x80>; 132 interrupts = <9 6>; 133 gpio-controller; 134 ngpios = <4>; 135 status = "disabled"; 136 #gpio-cells = <2>; 137 }; 138 gpio_prt10: gpio@40310500 { 139 compatible = "infineon,cat1-gpio"; 140 reg = <0x40310500 0x80>; 141 interrupts = <10 6>; 142 gpio-controller; 143 ngpios = <8>; 144 status = "disabled"; 145 #gpio-cells = <2>; 146 }; 147 gpio_prt11: gpio@40310580 { 148 compatible = "infineon,cat1-gpio"; 149 reg = <0x40310580 0x80>; 150 interrupts = <11 6>; 151 gpio-controller; 152 ngpios = <8>; 153 status = "disabled"; 154 #gpio-cells = <2>; 155 }; 156 gpio_prt12: gpio@40310600 { 157 compatible = "infineon,cat1-gpio"; 158 reg = <0x40310600 0x80>; 159 interrupts = <12 6>; 160 gpio-controller; 161 ngpios = <4>; 162 status = "disabled"; 163 #gpio-cells = <2>; 164 }; 165 gpio_prt14: gpio@40310700 { 166 compatible = "infineon,cat1-gpio"; 167 reg = <0x40310700 0x80>; 168 interrupts = <14 6>; 169 gpio-controller; 170 ngpios = <2>; 171 status = "disabled"; 172 #gpio-cells = <2>; 173 }; 174 }; 175 uid: device_uid@16000600 { 176 compatible = "infineon,cat1-uid"; 177 reg = <0x16000600 0xb>; 178 status = "disabled"; 179 }; 180 181 adc0: adc@409d0000 { 182 compatible = "infineon,cat1-adc"; 183 reg = <0x409d0000 0x10000>; 184 interrupts = <155 6>; 185 status = "disabled"; 186 }; 187 188 scb0: scb@40600000 { 189 compatible = "infineon,cat1-scb"; 190 reg = <0x40600000 0x10000>; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 interrupts = <39 6>; 194 status = "disabled"; 195 }; 196 scb1: scb@40610000 { 197 compatible = "infineon,cat1-scb"; 198 reg = <0x40610000 0x10000>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 interrupts = <40 6>; 202 status = "disabled"; 203 }; 204 scb2: scb@40620000 { 205 compatible = "infineon,cat1-scb"; 206 reg = <0x40620000 0x10000>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 interrupts = <41 6>; 210 status = "disabled"; 211 }; 212 scb3: scb@40630000 { 213 compatible = "infineon,cat1-scb"; 214 reg = <0x40630000 0x10000>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <42 6>; 218 status = "disabled"; 219 }; 220 scb4: scb@40640000 { 221 compatible = "infineon,cat1-scb"; 222 reg = <0x40640000 0x10000>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 interrupts = <43 6>; 226 status = "disabled"; 227 }; 228 scb5: scb@40650000 { 229 compatible = "infineon,cat1-scb"; 230 reg = <0x40650000 0x10000>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 interrupts = <44 6>; 234 status = "disabled"; 235 }; 236 scb6: scb@40660000 { 237 compatible = "infineon,cat1-scb"; 238 reg = <0x40660000 0x10000>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 interrupts = <18 6>; 242 status = "disabled"; 243 }; 244 245 }; 246}; 247
