1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
10#include "psoc6_03.dtsi"
11
12/ {
13	soc {
14		/delete-node/ gpio@40310080; // gpio_prt1
15		/delete-node/ gpio@40310180; // gpio_prt3
16		/delete-node/ gpio@40310200; // gpio_prt4
17		/delete-node/ gpio@40310400; // gpio_prt8
18		/delete-node/ gpio@40310600; // gpio_prt12
19		/delete-node/ gpio@40310680; // gpio_prt13
20		/delete-node/ gpio@40310700; // gpio_prt14
21
22		pinctrl: pinctrl@40300000 {
23			/* scb_i2c_scl */
24			/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
25				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
26			};
27			/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
28				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
29			};
30			/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
31				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
32			};
33			/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
34				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
35			};
36			/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
37				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
38			};
39			/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
40				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
41			};
42
43			/* scb_i2c_sda */
44			/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
45				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
46			};
47			/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
48				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
49			};
50			/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
51				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
52			};
53			/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
54				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
55			};
56			/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
57				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
58			};
59			/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
60				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
61			};
62
63			/* scb_uart_cts */
64			/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
65				pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
66			};
67			/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
68				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
69			};
70			/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
71				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
72			};
73			/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
74				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
75			};
76			/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
77				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
78			};
79			/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
80				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
81			};
82
83			/* scb_uart_rts */
84			/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
85				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
86			};
87			/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
88				pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
89			};
90			/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
91				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
92			};
93			/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
94				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
95			};
96			/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
97				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
98			};
99			/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
100				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
101			};
102			/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
103				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
104			};
105
106			/* scb_uart_rx */
107			/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
108				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
109			};
110			/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
111				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
112			};
113			/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
114				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
115			};
116			/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
117				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
118			};
119			/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
120				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
121			};
122
123			/* scb_uart_tx */
124			/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
125				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
126			};
127			/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
128				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
129			};
130			/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
131				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
132			};
133			/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
134				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
135			};
136			/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
137				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
138			};
139
140		};
141	};
142};
143