1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
10#include "psoc6_02.dtsi"
11
12/ {
13	soc {
14		/delete-node/ gpio@40310080; // gpio_prt1
15		/delete-node/ gpio@40310200; // gpio_prt4
16		/delete-node/ gpio@40310680; // gpio_prt13
17
18		pinctrl: pinctrl@40300000 {
19			/* scb_i2c_scl */
20			/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
21				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
22			};
23			/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
24				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
25			};
26			/omit-if-no-ref/ p2_4_scb9_i2c_scl: p2_4_scb9_i2c_scl {
27				pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_7)>;
28			};
29			/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
30				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
31			};
32			/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
33				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
34			};
35			/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
36				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>;
37			};
38			/omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl {
39				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
40			};
41			/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
42				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
43			};
44			/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
45				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
46			};
47			/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
48				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
49			};
50			/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
51				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
52			};
53			/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
54				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
55			};
56
57			/* scb_i2c_sda */
58			/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
59				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
60			};
61			/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
62				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
63			};
64			/omit-if-no-ref/ p2_5_scb9_i2c_sda: p2_5_scb9_i2c_sda {
65				pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_7)>;
66			};
67			/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
68				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
69			};
70			/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
71				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
72			};
73			/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
74				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>;
75			};
76			/omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda {
77				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
78			};
79			/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
80				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
81			};
82			/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
83				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
84			};
85			/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
86				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
87			};
88			/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
89				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
90			};
91			/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
92				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
93			};
94
95			/* scb_uart_cts */
96			/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
97				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
98			};
99			/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
100				pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
101			};
102			/omit-if-no-ref/ p2_7_scb9_uart_cts: p2_7_scb9_uart_cts {
103				pinmux = <DT_CAT1_PINMUX(2, 7, HSIOM_SEL_ACT_6)>;
104			};
105			/omit-if-no-ref/ p5_7_scb10_uart_cts: p5_7_scb10_uart_cts {
106				pinmux = <DT_CAT1_PINMUX(5, 7, HSIOM_SEL_ACT_6)>;
107			};
108			/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
109				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
110			};
111			/omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts {
112				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>;
113			};
114			/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
115				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
116			};
117			/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
118				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
119			};
120			/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
121				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
122			};
123			/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
124				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
125			};
126
127			/* scb_uart_rts */
128			/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
129				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
130			};
131			/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
132				pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
133			};
134			/omit-if-no-ref/ p2_6_scb9_uart_rts: p2_6_scb9_uart_rts {
135				pinmux = <DT_CAT1_PINMUX(2, 6, HSIOM_SEL_ACT_6)>;
136			};
137			/omit-if-no-ref/ p5_6_scb10_uart_rts: p5_6_scb10_uart_rts {
138				pinmux = <DT_CAT1_PINMUX(5, 6, HSIOM_SEL_ACT_6)>;
139			};
140			/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
141				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
142			};
143			/omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts {
144				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>;
145			};
146			/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
147				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
148			};
149			/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
150				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
151			};
152			/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
153				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
154			};
155			/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
156				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
157			};
158
159			/* scb_uart_rx */
160			/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
161				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
162			};
163			/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
164				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
165			};
166			/omit-if-no-ref/ p2_4_scb9_uart_rx: p2_4_scb9_uart_rx {
167				pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_6)>;
168			};
169			/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
170				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
171			};
172			/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
173				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
174			};
175			/omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx {
176				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>;
177			};
178			/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
179				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
180			};
181			/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
182				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
183			};
184			/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
185				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
186			};
187			/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
188				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
189			};
190			/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
191				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
192			};
193
194			/* scb_uart_tx */
195			/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
196				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
197			};
198			/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
199				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
200			};
201			/omit-if-no-ref/ p2_5_scb9_uart_tx: p2_5_scb9_uart_tx {
202				pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_6)>;
203			};
204			/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
205				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
206			};
207			/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
208				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
209			};
210			/omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx {
211				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>;
212			};
213			/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
214				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
215			};
216			/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
217				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
218			};
219			/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
220				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
221			};
222			/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
223				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
224			};
225			/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
226				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
227			};
228
229		};
230	};
231};
232