1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
10#include "psoc6_02.dtsi"
11
12/ {
13	soc {
14
15		pinctrl: pinctrl@40300000 {
16			/* scb_i2c_scl */
17			/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
18				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
19			};
20			/omit-if-no-ref/ p1_0_scb7_i2c_scl: p1_0_scb7_i2c_scl {
21				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_7)>;
22			};
23			/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
24				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
25			};
26			/omit-if-no-ref/ p2_4_scb9_i2c_scl: p2_4_scb9_i2c_scl {
27				pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_7)>;
28			};
29			/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
30				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
31			};
32			/omit-if-no-ref/ p4_0_scb7_i2c_scl: p4_0_scb7_i2c_scl {
33				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_7)>;
34			};
35			/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
36				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
37			};
38			/omit-if-no-ref/ p5_4_scb10_i2c_scl: p5_4_scb10_i2c_scl {
39				pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_7)>;
40			};
41			/omit-if-no-ref/ p6_0_scb3_i2c_scl: p6_0_scb3_i2c_scl {
42				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_7)>;
43			};
44			/omit-if-no-ref/ p6_0_scb8_i2c_scl: p6_0_scb8_i2c_scl {
45				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_DS_2)>;
46			};
47			/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
48				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>;
49			};
50			/omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl {
51				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
52			};
53			/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
54				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
55			};
56			/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
57				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
58			};
59			/omit-if-no-ref/ p8_4_scb11_i2c_scl: p8_4_scb11_i2c_scl {
60				pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_7)>;
61			};
62			/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
63				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
64			};
65			/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
66				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
67			};
68			/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
69				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
70			};
71			/omit-if-no-ref/ p12_0_scb6_i2c_scl: p12_0_scb6_i2c_scl {
72				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_7)>;
73			};
74			/omit-if-no-ref/ p13_0_scb6_i2c_scl: p13_0_scb6_i2c_scl {
75				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_7)>;
76			};
77			/omit-if-no-ref/ p13_4_scb12_i2c_scl: p13_4_scb12_i2c_scl {
78				pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_7)>;
79			};
80
81			/* scb_i2c_sda */
82			/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
83				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
84			};
85			/omit-if-no-ref/ p1_1_scb7_i2c_sda: p1_1_scb7_i2c_sda {
86				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_7)>;
87			};
88			/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
89				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
90			};
91			/omit-if-no-ref/ p2_5_scb9_i2c_sda: p2_5_scb9_i2c_sda {
92				pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_7)>;
93			};
94			/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
95				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
96			};
97			/omit-if-no-ref/ p4_1_scb7_i2c_sda: p4_1_scb7_i2c_sda {
98				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_7)>;
99			};
100			/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
101				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
102			};
103			/omit-if-no-ref/ p5_5_scb10_i2c_sda: p5_5_scb10_i2c_sda {
104				pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_7)>;
105			};
106			/omit-if-no-ref/ p6_1_scb3_i2c_sda: p6_1_scb3_i2c_sda {
107				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_7)>;
108			};
109			/omit-if-no-ref/ p6_1_scb8_i2c_sda: p6_1_scb8_i2c_sda {
110				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_DS_2)>;
111			};
112			/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
113				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>;
114			};
115			/omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda {
116				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
117			};
118			/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
119				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
120			};
121			/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
122				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
123			};
124			/omit-if-no-ref/ p8_5_scb11_i2c_sda: p8_5_scb11_i2c_sda {
125				pinmux = <DT_CAT1_PINMUX(8, 5, HSIOM_SEL_ACT_7)>;
126			};
127			/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
128				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
129			};
130			/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
131				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
132			};
133			/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
134				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
135			};
136			/omit-if-no-ref/ p12_1_scb6_i2c_sda: p12_1_scb6_i2c_sda {
137				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_7)>;
138			};
139			/omit-if-no-ref/ p13_1_scb6_i2c_sda: p13_1_scb6_i2c_sda {
140				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_7)>;
141			};
142			/omit-if-no-ref/ p13_5_scb12_i2c_sda: p13_5_scb12_i2c_sda {
143				pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_7)>;
144			};
145
146			/* scb_uart_cts */
147			/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
148				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
149			};
150			/omit-if-no-ref/ p1_3_scb7_uart_cts: p1_3_scb7_uart_cts {
151				pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_6)>;
152			};
153			/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
154				pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
155			};
156			/omit-if-no-ref/ p2_7_scb9_uart_cts: p2_7_scb9_uart_cts {
157				pinmux = <DT_CAT1_PINMUX(2, 7, HSIOM_SEL_ACT_6)>;
158			};
159			/omit-if-no-ref/ p3_3_scb2_uart_cts: p3_3_scb2_uart_cts {
160				pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>;
161			};
162			/omit-if-no-ref/ p4_3_scb7_uart_cts: p4_3_scb7_uart_cts {
163				pinmux = <DT_CAT1_PINMUX(4, 3, HSIOM_SEL_ACT_6)>;
164			};
165			/omit-if-no-ref/ p5_3_scb5_uart_cts: p5_3_scb5_uart_cts {
166				pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_6)>;
167			};
168			/omit-if-no-ref/ p5_7_scb10_uart_cts: p5_7_scb10_uart_cts {
169				pinmux = <DT_CAT1_PINMUX(5, 7, HSIOM_SEL_ACT_6)>;
170			};
171			/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
172				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
173			};
174			/omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts {
175				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>;
176			};
177			/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
178				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
179			};
180			/omit-if-no-ref/ p8_3_scb4_uart_cts: p8_3_scb4_uart_cts {
181				pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_6)>;
182			};
183			/omit-if-no-ref/ p8_7_scb11_uart_cts: p8_7_scb11_uart_cts {
184				pinmux = <DT_CAT1_PINMUX(8, 7, HSIOM_SEL_ACT_6)>;
185			};
186			/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
187				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
188			};
189			/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
190				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
191			};
192			/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
193				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
194			};
195			/omit-if-no-ref/ p12_3_scb6_uart_cts: p12_3_scb6_uart_cts {
196				pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_6)>;
197			};
198			/omit-if-no-ref/ p13_3_scb6_uart_cts: p13_3_scb6_uart_cts {
199				pinmux = <DT_CAT1_PINMUX(13, 3, HSIOM_SEL_ACT_6)>;
200			};
201			/omit-if-no-ref/ p13_7_scb12_uart_cts: p13_7_scb12_uart_cts {
202				pinmux = <DT_CAT1_PINMUX(13, 7, HSIOM_SEL_ACT_6)>;
203			};
204
205			/* scb_uart_rts */
206			/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
207				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
208			};
209			/omit-if-no-ref/ p1_2_scb7_uart_rts: p1_2_scb7_uart_rts {
210				pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_6)>;
211			};
212			/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
213				pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
214			};
215			/omit-if-no-ref/ p2_6_scb9_uart_rts: p2_6_scb9_uart_rts {
216				pinmux = <DT_CAT1_PINMUX(2, 6, HSIOM_SEL_ACT_6)>;
217			};
218			/omit-if-no-ref/ p3_2_scb2_uart_rts: p3_2_scb2_uart_rts {
219				pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_6)>;
220			};
221			/omit-if-no-ref/ p4_2_scb7_uart_rts: p4_2_scb7_uart_rts {
222				pinmux = <DT_CAT1_PINMUX(4, 2, HSIOM_SEL_ACT_6)>;
223			};
224			/omit-if-no-ref/ p5_2_scb5_uart_rts: p5_2_scb5_uart_rts {
225				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_6)>;
226			};
227			/omit-if-no-ref/ p5_6_scb10_uart_rts: p5_6_scb10_uart_rts {
228				pinmux = <DT_CAT1_PINMUX(5, 6, HSIOM_SEL_ACT_6)>;
229			};
230			/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
231				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
232			};
233			/omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts {
234				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>;
235			};
236			/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
237				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
238			};
239			/omit-if-no-ref/ p8_2_scb4_uart_rts: p8_2_scb4_uart_rts {
240				pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_6)>;
241			};
242			/omit-if-no-ref/ p8_6_scb11_uart_rts: p8_6_scb11_uart_rts {
243				pinmux = <DT_CAT1_PINMUX(8, 6, HSIOM_SEL_ACT_6)>;
244			};
245			/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
246				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
247			};
248			/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
249				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
250			};
251			/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
252				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
253			};
254			/omit-if-no-ref/ p12_2_scb6_uart_rts: p12_2_scb6_uart_rts {
255				pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_6)>;
256			};
257			/omit-if-no-ref/ p13_2_scb6_uart_rts: p13_2_scb6_uart_rts {
258				pinmux = <DT_CAT1_PINMUX(13, 2, HSIOM_SEL_ACT_6)>;
259			};
260			/omit-if-no-ref/ p13_6_scb12_uart_rts: p13_6_scb12_uart_rts {
261				pinmux = <DT_CAT1_PINMUX(13, 6, HSIOM_SEL_ACT_6)>;
262			};
263
264			/* scb_uart_rx */
265			/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
266				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
267			};
268			/omit-if-no-ref/ p1_0_scb7_uart_rx: p1_0_scb7_uart_rx {
269				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
270			};
271			/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
272				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
273			};
274			/omit-if-no-ref/ p2_4_scb9_uart_rx: p2_4_scb9_uart_rx {
275				pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_6)>;
276			};
277			/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
278				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
279			};
280			/omit-if-no-ref/ p4_0_scb7_uart_rx: p4_0_scb7_uart_rx {
281				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_6)>;
282			};
283			/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
284				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
285			};
286			/omit-if-no-ref/ p5_4_scb10_uart_rx: p5_4_scb10_uart_rx {
287				pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_6)>;
288			};
289			/omit-if-no-ref/ p6_0_scb3_uart_rx: p6_0_scb3_uart_rx {
290				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_6)>;
291			};
292			/omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx {
293				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>;
294			};
295			/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
296				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
297			};
298			/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
299				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
300			};
301			/omit-if-no-ref/ p8_4_scb11_uart_rx: p8_4_scb11_uart_rx {
302				pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_6)>;
303			};
304			/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
305				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
306			};
307			/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
308				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
309			};
310			/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
311				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
312			};
313			/omit-if-no-ref/ p12_0_scb6_uart_rx: p12_0_scb6_uart_rx {
314				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_6)>;
315			};
316			/omit-if-no-ref/ p13_0_scb6_uart_rx: p13_0_scb6_uart_rx {
317				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_6)>;
318			};
319			/omit-if-no-ref/ p13_4_scb12_uart_rx: p13_4_scb12_uart_rx {
320				pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_6)>;
321			};
322
323			/* scb_uart_tx */
324			/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
325				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
326			};
327			/omit-if-no-ref/ p1_1_scb7_uart_tx: p1_1_scb7_uart_tx {
328				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
329			};
330			/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
331				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
332			};
333			/omit-if-no-ref/ p2_5_scb9_uart_tx: p2_5_scb9_uart_tx {
334				pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_6)>;
335			};
336			/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
337				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
338			};
339			/omit-if-no-ref/ p4_1_scb7_uart_tx: p4_1_scb7_uart_tx {
340				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_6)>;
341			};
342			/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
343				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
344			};
345			/omit-if-no-ref/ p5_5_scb10_uart_tx: p5_5_scb10_uart_tx {
346				pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_6)>;
347			};
348			/omit-if-no-ref/ p6_1_scb3_uart_tx: p6_1_scb3_uart_tx {
349				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_6)>;
350			};
351			/omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx {
352				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>;
353			};
354			/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
355				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
356			};
357			/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
358				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
359			};
360			/omit-if-no-ref/ p8_5_scb11_uart_tx: p8_5_scb11_uart_tx {
361				pinmux = <DT_CAT1_PINMUX(8, 5, HSIOM_SEL_ACT_6)>;
362			};
363			/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
364				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
365			};
366			/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
367				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
368			};
369			/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
370				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
371			};
372			/omit-if-no-ref/ p12_1_scb6_uart_tx: p12_1_scb6_uart_tx {
373				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_6)>;
374			};
375			/omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx {
376				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_6)>;
377			};
378			/omit-if-no-ref/ p13_5_scb12_uart_tx: p13_5_scb12_uart_tx {
379				pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_6)>;
380			};
381
382		};
383	};
384};
385