1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
10#include "psoc6_02.dtsi"
11
12/ {
13	soc {
14		pinctrl: pinctrl@40300000 {
15			/* scb_i2c_scl */
16			/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
17				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
18			};
19			/omit-if-no-ref/ p1_0_scb7_i2c_scl: p1_0_scb7_i2c_scl {
20				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_7)>;
21			};
22			/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
23				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
24			};
25			/omit-if-no-ref/ p2_4_scb9_i2c_scl: p2_4_scb9_i2c_scl {
26				pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_7)>;
27			};
28			/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
29				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
30			};
31			/omit-if-no-ref/ p4_0_scb7_i2c_scl: p4_0_scb7_i2c_scl {
32				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_7)>;
33			};
34			/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
35				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
36			};
37			/omit-if-no-ref/ p5_4_scb10_i2c_scl: p5_4_scb10_i2c_scl {
38				pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_7)>;
39			};
40			/omit-if-no-ref/ p6_0_scb3_i2c_scl: p6_0_scb3_i2c_scl {
41				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_7)>;
42			};
43			/omit-if-no-ref/ p6_0_scb8_i2c_scl: p6_0_scb8_i2c_scl {
44				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_DS_2)>;
45			};
46			/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
47				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>;
48			};
49			/omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl {
50				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
51			};
52			/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
53				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
54			};
55			/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
56				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
57			};
58			/omit-if-no-ref/ p8_4_scb11_i2c_scl: p8_4_scb11_i2c_scl {
59				pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_7)>;
60			};
61			/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
62				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
63			};
64			/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
65				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
66			};
67			/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
68				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
69			};
70			/omit-if-no-ref/ p12_0_scb6_i2c_scl: p12_0_scb6_i2c_scl {
71				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_7)>;
72			};
73			/omit-if-no-ref/ p13_0_scb6_i2c_scl: p13_0_scb6_i2c_scl {
74				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_7)>;
75			};
76			/omit-if-no-ref/ p13_4_scb12_i2c_scl: p13_4_scb12_i2c_scl {
77				pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_7)>;
78			};
79
80			/* scb_i2c_sda */
81			/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
82				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
83			};
84			/omit-if-no-ref/ p1_1_scb7_i2c_sda: p1_1_scb7_i2c_sda {
85				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_7)>;
86			};
87			/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
88				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
89			};
90			/omit-if-no-ref/ p2_5_scb9_i2c_sda: p2_5_scb9_i2c_sda {
91				pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_7)>;
92			};
93			/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
94				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
95			};
96			/omit-if-no-ref/ p4_1_scb7_i2c_sda: p4_1_scb7_i2c_sda {
97				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_7)>;
98			};
99			/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
100				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
101			};
102			/omit-if-no-ref/ p5_5_scb10_i2c_sda: p5_5_scb10_i2c_sda {
103				pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_7)>;
104			};
105			/omit-if-no-ref/ p6_1_scb3_i2c_sda: p6_1_scb3_i2c_sda {
106				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_7)>;
107			};
108			/omit-if-no-ref/ p6_1_scb8_i2c_sda: p6_1_scb8_i2c_sda {
109				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_DS_2)>;
110			};
111			/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
112				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>;
113			};
114			/omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda {
115				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
116			};
117			/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
118				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
119			};
120			/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
121				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
122			};
123			/omit-if-no-ref/ p8_5_scb11_i2c_sda: p8_5_scb11_i2c_sda {
124				pinmux = <DT_CAT1_PINMUX(8, 5, HSIOM_SEL_ACT_7)>;
125			};
126			/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
127				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
128			};
129			/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
130				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
131			};
132			/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
133				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
134			};
135			/omit-if-no-ref/ p12_1_scb6_i2c_sda: p12_1_scb6_i2c_sda {
136				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_7)>;
137			};
138			/omit-if-no-ref/ p13_1_scb6_i2c_sda: p13_1_scb6_i2c_sda {
139				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_7)>;
140			};
141			/omit-if-no-ref/ p13_5_scb12_i2c_sda: p13_5_scb12_i2c_sda {
142				pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_7)>;
143			};
144
145			/* scb_uart_cts */
146			/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
147				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
148			};
149			/omit-if-no-ref/ p1_3_scb7_uart_cts: p1_3_scb7_uart_cts {
150				pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_6)>;
151			};
152			/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
153				pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
154			};
155			/omit-if-no-ref/ p2_7_scb9_uart_cts: p2_7_scb9_uart_cts {
156				pinmux = <DT_CAT1_PINMUX(2, 7, HSIOM_SEL_ACT_6)>;
157			};
158			/omit-if-no-ref/ p3_3_scb2_uart_cts: p3_3_scb2_uart_cts {
159				pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>;
160			};
161			/omit-if-no-ref/ p5_3_scb5_uart_cts: p5_3_scb5_uart_cts {
162				pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_6)>;
163			};
164			/omit-if-no-ref/ p5_7_scb10_uart_cts: p5_7_scb10_uart_cts {
165				pinmux = <DT_CAT1_PINMUX(5, 7, HSIOM_SEL_ACT_6)>;
166			};
167			/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
168				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
169			};
170			/omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts {
171				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>;
172			};
173			/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
174				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
175			};
176			/omit-if-no-ref/ p8_3_scb4_uart_cts: p8_3_scb4_uart_cts {
177				pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_6)>;
178			};
179			/omit-if-no-ref/ p8_7_scb11_uart_cts: p8_7_scb11_uart_cts {
180				pinmux = <DT_CAT1_PINMUX(8, 7, HSIOM_SEL_ACT_6)>;
181			};
182			/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
183				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
184			};
185			/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
186				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
187			};
188			/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
189				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
190			};
191			/omit-if-no-ref/ p12_3_scb6_uart_cts: p12_3_scb6_uart_cts {
192				pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_6)>;
193			};
194			/omit-if-no-ref/ p13_3_scb6_uart_cts: p13_3_scb6_uart_cts {
195				pinmux = <DT_CAT1_PINMUX(13, 3, HSIOM_SEL_ACT_6)>;
196			};
197			/omit-if-no-ref/ p13_7_scb12_uart_cts: p13_7_scb12_uart_cts {
198				pinmux = <DT_CAT1_PINMUX(13, 7, HSIOM_SEL_ACT_6)>;
199			};
200
201			/* scb_uart_rts */
202			/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
203				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
204			};
205			/omit-if-no-ref/ p1_2_scb7_uart_rts: p1_2_scb7_uart_rts {
206				pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_6)>;
207			};
208			/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
209				pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
210			};
211			/omit-if-no-ref/ p2_6_scb9_uart_rts: p2_6_scb9_uart_rts {
212				pinmux = <DT_CAT1_PINMUX(2, 6, HSIOM_SEL_ACT_6)>;
213			};
214			/omit-if-no-ref/ p3_2_scb2_uart_rts: p3_2_scb2_uart_rts {
215				pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_6)>;
216			};
217			/omit-if-no-ref/ p5_2_scb5_uart_rts: p5_2_scb5_uart_rts {
218				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_6)>;
219			};
220			/omit-if-no-ref/ p5_6_scb10_uart_rts: p5_6_scb10_uart_rts {
221				pinmux = <DT_CAT1_PINMUX(5, 6, HSIOM_SEL_ACT_6)>;
222			};
223			/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
224				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
225			};
226			/omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts {
227				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>;
228			};
229			/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
230				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
231			};
232			/omit-if-no-ref/ p8_2_scb4_uart_rts: p8_2_scb4_uart_rts {
233				pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_6)>;
234			};
235			/omit-if-no-ref/ p8_6_scb11_uart_rts: p8_6_scb11_uart_rts {
236				pinmux = <DT_CAT1_PINMUX(8, 6, HSIOM_SEL_ACT_6)>;
237			};
238			/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
239				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
240			};
241			/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
242				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
243			};
244			/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
245				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
246			};
247			/omit-if-no-ref/ p12_2_scb6_uart_rts: p12_2_scb6_uart_rts {
248				pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_6)>;
249			};
250			/omit-if-no-ref/ p13_2_scb6_uart_rts: p13_2_scb6_uart_rts {
251				pinmux = <DT_CAT1_PINMUX(13, 2, HSIOM_SEL_ACT_6)>;
252			};
253			/omit-if-no-ref/ p13_6_scb12_uart_rts: p13_6_scb12_uart_rts {
254				pinmux = <DT_CAT1_PINMUX(13, 6, HSIOM_SEL_ACT_6)>;
255			};
256
257			/* scb_uart_rx */
258			/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
259				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
260			};
261			/omit-if-no-ref/ p1_0_scb7_uart_rx: p1_0_scb7_uart_rx {
262				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
263			};
264			/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
265				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
266			};
267			/omit-if-no-ref/ p2_4_scb9_uart_rx: p2_4_scb9_uart_rx {
268				pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_6)>;
269			};
270			/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
271				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
272			};
273			/omit-if-no-ref/ p4_0_scb7_uart_rx: p4_0_scb7_uart_rx {
274				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_6)>;
275			};
276			/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
277				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
278			};
279			/omit-if-no-ref/ p5_4_scb10_uart_rx: p5_4_scb10_uart_rx {
280				pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_6)>;
281			};
282			/omit-if-no-ref/ p6_0_scb3_uart_rx: p6_0_scb3_uart_rx {
283				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_6)>;
284			};
285			/omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx {
286				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>;
287			};
288			/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
289				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
290			};
291			/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
292				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
293			};
294			/omit-if-no-ref/ p8_4_scb11_uart_rx: p8_4_scb11_uart_rx {
295				pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_6)>;
296			};
297			/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
298				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
299			};
300			/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
301				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
302			};
303			/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
304				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
305			};
306			/omit-if-no-ref/ p12_0_scb6_uart_rx: p12_0_scb6_uart_rx {
307				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_6)>;
308			};
309			/omit-if-no-ref/ p13_0_scb6_uart_rx: p13_0_scb6_uart_rx {
310				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_6)>;
311			};
312			/omit-if-no-ref/ p13_4_scb12_uart_rx: p13_4_scb12_uart_rx {
313				pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_6)>;
314			};
315
316			/* scb_uart_tx */
317			/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
318				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
319			};
320			/omit-if-no-ref/ p1_1_scb7_uart_tx: p1_1_scb7_uart_tx {
321				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
322			};
323			/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
324				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
325			};
326			/omit-if-no-ref/ p2_5_scb9_uart_tx: p2_5_scb9_uart_tx {
327				pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_6)>;
328			};
329			/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
330				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
331			};
332			/omit-if-no-ref/ p4_1_scb7_uart_tx: p4_1_scb7_uart_tx {
333				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_6)>;
334			};
335			/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
336				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
337			};
338			/omit-if-no-ref/ p5_5_scb10_uart_tx: p5_5_scb10_uart_tx {
339				pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_6)>;
340			};
341			/omit-if-no-ref/ p6_1_scb3_uart_tx: p6_1_scb3_uart_tx {
342				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_6)>;
343			};
344			/omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx {
345				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>;
346			};
347			/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
348				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
349			};
350			/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
351				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
352			};
353			/omit-if-no-ref/ p8_5_scb11_uart_tx: p8_5_scb11_uart_tx {
354				pinmux = <DT_CAT1_PINMUX(8, 5, HSIOM_SEL_ACT_6)>;
355			};
356			/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
357				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
358			};
359			/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
360				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
361			};
362			/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
363				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
364			};
365			/omit-if-no-ref/ p12_1_scb6_uart_tx: p12_1_scb6_uart_tx {
366				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_6)>;
367			};
368			/omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx {
369				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_6)>;
370			};
371			/omit-if-no-ref/ p13_5_scb12_uart_tx: p13_5_scb12_uart_tx {
372				pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_6)>;
373			};
374
375			/* tcpwm_line */
376			/omit-if-no-ref/ p0_0_tcpwm0_line: p0_0_tcpwm0_line {
377				pinmux = <DT_CAT1_PINMUX(0, 0, HSIOM_SEL_ACT_0)>;
378			};
379			/omit-if-no-ref/ p0_0_tcpwm1_line: p0_0_tcpwm1_line {
380				pinmux = <DT_CAT1_PINMUX(0, 0, HSIOM_SEL_ACT_1)>;
381			};
382			/omit-if-no-ref/ p0_2_tcpwm0_line: p0_2_tcpwm0_line {
383				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_0)>;
384			};
385			/omit-if-no-ref/ p0_2_tcpwm1_line: p0_2_tcpwm1_line {
386				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_1)>;
387			};
388			/omit-if-no-ref/ p0_4_tcpwm0_line: p0_4_tcpwm0_line {
389				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_0)>;
390			};
391			/omit-if-no-ref/ p0_4_tcpwm1_line: p0_4_tcpwm1_line {
392				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_1)>;
393			};
394			/omit-if-no-ref/ p1_0_tcpwm0_line: p1_0_tcpwm0_line {
395				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_0)>;
396			};
397			/omit-if-no-ref/ p1_0_tcpwm1_line: p1_0_tcpwm1_line {
398				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_1)>;
399			};
400			/omit-if-no-ref/ p1_2_tcpwm0_line: p1_2_tcpwm0_line {
401				pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_0)>;
402			};
403			/omit-if-no-ref/ p1_2_tcpwm1_line: p1_2_tcpwm1_line {
404				pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_1)>;
405			};
406			/omit-if-no-ref/ p1_4_tcpwm0_line: p1_4_tcpwm0_line {
407				pinmux = <DT_CAT1_PINMUX(1, 4, HSIOM_SEL_ACT_0)>;
408			};
409			/omit-if-no-ref/ p1_4_tcpwm1_line: p1_4_tcpwm1_line {
410				pinmux = <DT_CAT1_PINMUX(1, 4, HSIOM_SEL_ACT_1)>;
411			};
412			/omit-if-no-ref/ p2_0_tcpwm0_line: p2_0_tcpwm0_line {
413				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_0)>;
414			};
415			/omit-if-no-ref/ p2_0_tcpwm1_line: p2_0_tcpwm1_line {
416				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_1)>;
417			};
418			/omit-if-no-ref/ p2_2_tcpwm0_line: p2_2_tcpwm0_line {
419				pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_0)>;
420			};
421			/omit-if-no-ref/ p2_2_tcpwm1_line: p2_2_tcpwm1_line {
422				pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_1)>;
423			};
424			/omit-if-no-ref/ p2_4_tcpwm0_line: p2_4_tcpwm0_line {
425				pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_0)>;
426			};
427			/omit-if-no-ref/ p2_4_tcpwm1_line: p2_4_tcpwm1_line {
428				pinmux = <DT_CAT1_PINMUX(2, 4, HSIOM_SEL_ACT_1)>;
429			};
430			/omit-if-no-ref/ p2_6_tcpwm0_line: p2_6_tcpwm0_line {
431				pinmux = <DT_CAT1_PINMUX(2, 6, HSIOM_SEL_ACT_0)>;
432			};
433			/omit-if-no-ref/ p2_6_tcpwm1_line: p2_6_tcpwm1_line {
434				pinmux = <DT_CAT1_PINMUX(2, 6, HSIOM_SEL_ACT_1)>;
435			};
436			/omit-if-no-ref/ p3_0_tcpwm0_line: p3_0_tcpwm0_line {
437				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_0)>;
438			};
439			/omit-if-no-ref/ p3_0_tcpwm1_line: p3_0_tcpwm1_line {
440				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_1)>;
441			};
442			/omit-if-no-ref/ p3_2_tcpwm0_line: p3_2_tcpwm0_line {
443				pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_0)>;
444			};
445			/omit-if-no-ref/ p3_2_tcpwm1_line: p3_2_tcpwm1_line {
446				pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_1)>;
447			};
448			/omit-if-no-ref/ p3_4_tcpwm0_line: p3_4_tcpwm0_line {
449				pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_0)>;
450			};
451			/omit-if-no-ref/ p3_4_tcpwm1_line: p3_4_tcpwm1_line {
452				pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_1)>;
453			};
454			/omit-if-no-ref/ p4_0_tcpwm0_line: p4_0_tcpwm0_line {
455				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_0)>;
456			};
457			/omit-if-no-ref/ p4_0_tcpwm1_line: p4_0_tcpwm1_line {
458				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_1)>;
459			};
460			/omit-if-no-ref/ p5_0_tcpwm0_line: p5_0_tcpwm0_line {
461				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_0)>;
462			};
463			/omit-if-no-ref/ p5_0_tcpwm1_line: p5_0_tcpwm1_line {
464				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_1)>;
465			};
466			/omit-if-no-ref/ p5_2_tcpwm0_line: p5_2_tcpwm0_line {
467				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_0)>;
468			};
469			/omit-if-no-ref/ p5_2_tcpwm1_line: p5_2_tcpwm1_line {
470				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_1)>;
471			};
472			/omit-if-no-ref/ p5_4_tcpwm0_line: p5_4_tcpwm0_line {
473				pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_0)>;
474			};
475			/omit-if-no-ref/ p5_4_tcpwm1_line: p5_4_tcpwm1_line {
476				pinmux = <DT_CAT1_PINMUX(5, 4, HSIOM_SEL_ACT_1)>;
477			};
478			/omit-if-no-ref/ p5_6_tcpwm0_line: p5_6_tcpwm0_line {
479				pinmux = <DT_CAT1_PINMUX(5, 6, HSIOM_SEL_ACT_0)>;
480			};
481			/omit-if-no-ref/ p5_6_tcpwm1_line: p5_6_tcpwm1_line {
482				pinmux = <DT_CAT1_PINMUX(5, 6, HSIOM_SEL_ACT_1)>;
483			};
484			/omit-if-no-ref/ p6_0_tcpwm0_line: p6_0_tcpwm0_line {
485				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_0)>;
486			};
487			/omit-if-no-ref/ p6_0_tcpwm1_line: p6_0_tcpwm1_line {
488				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_1)>;
489			};
490			/omit-if-no-ref/ p6_2_tcpwm0_line: p6_2_tcpwm0_line {
491				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_0)>;
492			};
493			/omit-if-no-ref/ p6_2_tcpwm1_line: p6_2_tcpwm1_line {
494				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_1)>;
495			};
496			/omit-if-no-ref/ p6_4_tcpwm0_line: p6_4_tcpwm0_line {
497				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_0)>;
498			};
499			/omit-if-no-ref/ p6_4_tcpwm1_line: p6_4_tcpwm1_line {
500				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_1)>;
501			};
502			/omit-if-no-ref/ p6_6_tcpwm0_line: p6_6_tcpwm0_line {
503				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_0)>;
504			};
505			/omit-if-no-ref/ p6_6_tcpwm1_line: p6_6_tcpwm1_line {
506				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_1)>;
507			};
508			/omit-if-no-ref/ p7_0_tcpwm0_line: p7_0_tcpwm0_line {
509				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_0)>;
510			};
511			/omit-if-no-ref/ p7_0_tcpwm1_line: p7_0_tcpwm1_line {
512				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_1)>;
513			};
514			/omit-if-no-ref/ p7_2_tcpwm0_line: p7_2_tcpwm0_line {
515				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_0)>;
516			};
517			/omit-if-no-ref/ p7_2_tcpwm1_line: p7_2_tcpwm1_line {
518				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_1)>;
519			};
520			/omit-if-no-ref/ p7_4_tcpwm0_line: p7_4_tcpwm0_line {
521				pinmux = <DT_CAT1_PINMUX(7, 4, HSIOM_SEL_ACT_0)>;
522			};
523			/omit-if-no-ref/ p7_4_tcpwm1_line: p7_4_tcpwm1_line {
524				pinmux = <DT_CAT1_PINMUX(7, 4, HSIOM_SEL_ACT_1)>;
525			};
526			/omit-if-no-ref/ p7_6_tcpwm0_line: p7_6_tcpwm0_line {
527				pinmux = <DT_CAT1_PINMUX(7, 6, HSIOM_SEL_ACT_0)>;
528			};
529			/omit-if-no-ref/ p7_6_tcpwm1_line: p7_6_tcpwm1_line {
530				pinmux = <DT_CAT1_PINMUX(7, 6, HSIOM_SEL_ACT_1)>;
531			};
532			/omit-if-no-ref/ p8_0_tcpwm0_line: p8_0_tcpwm0_line {
533				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_0)>;
534			};
535			/omit-if-no-ref/ p8_0_tcpwm1_line: p8_0_tcpwm1_line {
536				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_1)>;
537			};
538			/omit-if-no-ref/ p8_2_tcpwm0_line: p8_2_tcpwm0_line {
539				pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_0)>;
540			};
541			/omit-if-no-ref/ p8_2_tcpwm1_line: p8_2_tcpwm1_line {
542				pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_1)>;
543			};
544			/omit-if-no-ref/ p8_4_tcpwm0_line: p8_4_tcpwm0_line {
545				pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_0)>;
546			};
547			/omit-if-no-ref/ p8_4_tcpwm1_line: p8_4_tcpwm1_line {
548				pinmux = <DT_CAT1_PINMUX(8, 4, HSIOM_SEL_ACT_1)>;
549			};
550			/omit-if-no-ref/ p8_6_tcpwm0_line: p8_6_tcpwm0_line {
551				pinmux = <DT_CAT1_PINMUX(8, 6, HSIOM_SEL_ACT_0)>;
552			};
553			/omit-if-no-ref/ p8_6_tcpwm1_line: p8_6_tcpwm1_line {
554				pinmux = <DT_CAT1_PINMUX(8, 6, HSIOM_SEL_ACT_1)>;
555			};
556			/omit-if-no-ref/ p9_0_tcpwm0_line: p9_0_tcpwm0_line {
557				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_0)>;
558			};
559			/omit-if-no-ref/ p9_0_tcpwm1_line: p9_0_tcpwm1_line {
560				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_1)>;
561			};
562			/omit-if-no-ref/ p9_2_tcpwm0_line: p9_2_tcpwm0_line {
563				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_0)>;
564			};
565			/omit-if-no-ref/ p9_2_tcpwm1_line: p9_2_tcpwm1_line {
566				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_1)>;
567			};
568			/omit-if-no-ref/ p9_4_tcpwm0_line: p9_4_tcpwm0_line {
569				pinmux = <DT_CAT1_PINMUX(9, 4, HSIOM_SEL_ACT_0)>;
570			};
571			/omit-if-no-ref/ p9_4_tcpwm1_line: p9_4_tcpwm1_line {
572				pinmux = <DT_CAT1_PINMUX(9, 4, HSIOM_SEL_ACT_1)>;
573			};
574			/omit-if-no-ref/ p9_6_tcpwm0_line: p9_6_tcpwm0_line {
575				pinmux = <DT_CAT1_PINMUX(9, 6, HSIOM_SEL_ACT_0)>;
576			};
577			/omit-if-no-ref/ p9_6_tcpwm1_line: p9_6_tcpwm1_line {
578				pinmux = <DT_CAT1_PINMUX(9, 6, HSIOM_SEL_ACT_1)>;
579			};
580			/omit-if-no-ref/ p10_0_tcpwm0_line: p10_0_tcpwm0_line {
581				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_0)>;
582			};
583			/omit-if-no-ref/ p10_0_tcpwm1_line: p10_0_tcpwm1_line {
584				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_1)>;
585			};
586			/omit-if-no-ref/ p10_2_tcpwm0_line: p10_2_tcpwm0_line {
587				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_0)>;
588			};
589			/omit-if-no-ref/ p10_2_tcpwm1_line: p10_2_tcpwm1_line {
590				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_1)>;
591			};
592			/omit-if-no-ref/ p10_4_tcpwm0_line: p10_4_tcpwm0_line {
593				pinmux = <DT_CAT1_PINMUX(10, 4, HSIOM_SEL_ACT_0)>;
594			};
595			/omit-if-no-ref/ p10_4_tcpwm1_line: p10_4_tcpwm1_line {
596				pinmux = <DT_CAT1_PINMUX(10, 4, HSIOM_SEL_ACT_1)>;
597			};
598			/omit-if-no-ref/ p10_6_tcpwm0_line: p10_6_tcpwm0_line {
599				pinmux = <DT_CAT1_PINMUX(10, 6, HSIOM_SEL_ACT_0)>;
600			};
601			/omit-if-no-ref/ p10_6_tcpwm1_line: p10_6_tcpwm1_line {
602				pinmux = <DT_CAT1_PINMUX(10, 6, HSIOM_SEL_ACT_1)>;
603			};
604			/omit-if-no-ref/ p11_0_tcpwm0_line: p11_0_tcpwm0_line {
605				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_0)>;
606			};
607			/omit-if-no-ref/ p11_0_tcpwm1_line: p11_0_tcpwm1_line {
608				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_1)>;
609			};
610			/omit-if-no-ref/ p11_2_tcpwm0_line: p11_2_tcpwm0_line {
611				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_0)>;
612			};
613			/omit-if-no-ref/ p11_2_tcpwm1_line: p11_2_tcpwm1_line {
614				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_1)>;
615			};
616			/omit-if-no-ref/ p11_4_tcpwm0_line: p11_4_tcpwm0_line {
617				pinmux = <DT_CAT1_PINMUX(11, 4, HSIOM_SEL_ACT_0)>;
618			};
619			/omit-if-no-ref/ p11_4_tcpwm1_line: p11_4_tcpwm1_line {
620				pinmux = <DT_CAT1_PINMUX(11, 4, HSIOM_SEL_ACT_1)>;
621			};
622			/omit-if-no-ref/ p12_0_tcpwm0_line: p12_0_tcpwm0_line {
623				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_0)>;
624			};
625			/omit-if-no-ref/ p12_0_tcpwm1_line: p12_0_tcpwm1_line {
626				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_1)>;
627			};
628			/omit-if-no-ref/ p12_2_tcpwm0_line: p12_2_tcpwm0_line {
629				pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_0)>;
630			};
631			/omit-if-no-ref/ p12_2_tcpwm1_line: p12_2_tcpwm1_line {
632				pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_1)>;
633			};
634			/omit-if-no-ref/ p12_4_tcpwm0_line: p12_4_tcpwm0_line {
635				pinmux = <DT_CAT1_PINMUX(12, 4, HSIOM_SEL_ACT_0)>;
636			};
637			/omit-if-no-ref/ p12_4_tcpwm1_line: p12_4_tcpwm1_line {
638				pinmux = <DT_CAT1_PINMUX(12, 4, HSIOM_SEL_ACT_1)>;
639			};
640			/omit-if-no-ref/ p12_6_tcpwm0_line: p12_6_tcpwm0_line {
641				pinmux = <DT_CAT1_PINMUX(12, 6, HSIOM_SEL_ACT_0)>;
642			};
643			/omit-if-no-ref/ p12_6_tcpwm1_line: p12_6_tcpwm1_line {
644				pinmux = <DT_CAT1_PINMUX(12, 6, HSIOM_SEL_ACT_1)>;
645			};
646			/omit-if-no-ref/ p13_0_tcpwm0_line: p13_0_tcpwm0_line {
647				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_0)>;
648			};
649			/omit-if-no-ref/ p13_0_tcpwm1_line: p13_0_tcpwm1_line {
650				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_1)>;
651			};
652			/omit-if-no-ref/ p13_2_tcpwm0_line: p13_2_tcpwm0_line {
653				pinmux = <DT_CAT1_PINMUX(13, 2, HSIOM_SEL_ACT_0)>;
654			};
655			/omit-if-no-ref/ p13_2_tcpwm1_line: p13_2_tcpwm1_line {
656				pinmux = <DT_CAT1_PINMUX(13, 2, HSIOM_SEL_ACT_1)>;
657			};
658			/omit-if-no-ref/ p13_4_tcpwm0_line: p13_4_tcpwm0_line {
659				pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_0)>;
660			};
661			/omit-if-no-ref/ p13_4_tcpwm1_line: p13_4_tcpwm1_line {
662				pinmux = <DT_CAT1_PINMUX(13, 4, HSIOM_SEL_ACT_1)>;
663			};
664			/omit-if-no-ref/ p13_6_tcpwm0_line: p13_6_tcpwm0_line {
665				pinmux = <DT_CAT1_PINMUX(13, 6, HSIOM_SEL_ACT_0)>;
666			};
667			/omit-if-no-ref/ p13_6_tcpwm1_line: p13_6_tcpwm1_line {
668				pinmux = <DT_CAT1_PINMUX(13, 6, HSIOM_SEL_ACT_1)>;
669			};
670
671			/* tcpwm_line_compl */
672			/omit-if-no-ref/ p0_1_tcpwm0_line_compl: p0_1_tcpwm0_line_compl {
673				pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_0)>;
674			};
675			/omit-if-no-ref/ p0_1_tcpwm1_line_compl: p0_1_tcpwm1_line_compl {
676				pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_ACT_1)>;
677			};
678			/omit-if-no-ref/ p0_3_tcpwm0_line_compl: p0_3_tcpwm0_line_compl {
679				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_0)>;
680			};
681			/omit-if-no-ref/ p0_3_tcpwm1_line_compl: p0_3_tcpwm1_line_compl {
682				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_1)>;
683			};
684			/omit-if-no-ref/ p0_5_tcpwm0_line_compl: p0_5_tcpwm0_line_compl {
685				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_0)>;
686			};
687			/omit-if-no-ref/ p0_5_tcpwm1_line_compl: p0_5_tcpwm1_line_compl {
688				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_1)>;
689			};
690			/omit-if-no-ref/ p1_1_tcpwm0_line_compl: p1_1_tcpwm0_line_compl {
691				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_0)>;
692			};
693			/omit-if-no-ref/ p1_1_tcpwm1_line_compl: p1_1_tcpwm1_line_compl {
694				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_1)>;
695			};
696			/omit-if-no-ref/ p1_3_tcpwm0_line_compl: p1_3_tcpwm0_line_compl {
697				pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_0)>;
698			};
699			/omit-if-no-ref/ p1_3_tcpwm1_line_compl: p1_3_tcpwm1_line_compl {
700				pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_1)>;
701			};
702			/omit-if-no-ref/ p1_5_tcpwm0_line_compl: p1_5_tcpwm0_line_compl {
703				pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_0)>;
704			};
705			/omit-if-no-ref/ p1_5_tcpwm1_line_compl: p1_5_tcpwm1_line_compl {
706				pinmux = <DT_CAT1_PINMUX(1, 5, HSIOM_SEL_ACT_1)>;
707			};
708			/omit-if-no-ref/ p2_1_tcpwm0_line_compl: p2_1_tcpwm0_line_compl {
709				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_0)>;
710			};
711			/omit-if-no-ref/ p2_1_tcpwm1_line_compl: p2_1_tcpwm1_line_compl {
712				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_1)>;
713			};
714			/omit-if-no-ref/ p2_3_tcpwm0_line_compl: p2_3_tcpwm0_line_compl {
715				pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_0)>;
716			};
717			/omit-if-no-ref/ p2_3_tcpwm1_line_compl: p2_3_tcpwm1_line_compl {
718				pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_1)>;
719			};
720			/omit-if-no-ref/ p2_5_tcpwm0_line_compl: p2_5_tcpwm0_line_compl {
721				pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_0)>;
722			};
723			/omit-if-no-ref/ p2_5_tcpwm1_line_compl: p2_5_tcpwm1_line_compl {
724				pinmux = <DT_CAT1_PINMUX(2, 5, HSIOM_SEL_ACT_1)>;
725			};
726			/omit-if-no-ref/ p2_7_tcpwm0_line_compl: p2_7_tcpwm0_line_compl {
727				pinmux = <DT_CAT1_PINMUX(2, 7, HSIOM_SEL_ACT_0)>;
728			};
729			/omit-if-no-ref/ p2_7_tcpwm1_line_compl: p2_7_tcpwm1_line_compl {
730				pinmux = <DT_CAT1_PINMUX(2, 7, HSIOM_SEL_ACT_1)>;
731			};
732			/omit-if-no-ref/ p3_1_tcpwm0_line_compl: p3_1_tcpwm0_line_compl {
733				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_0)>;
734			};
735			/omit-if-no-ref/ p3_1_tcpwm1_line_compl: p3_1_tcpwm1_line_compl {
736				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_1)>;
737			};
738			/omit-if-no-ref/ p3_3_tcpwm0_line_compl: p3_3_tcpwm0_line_compl {
739				pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_0)>;
740			};
741			/omit-if-no-ref/ p3_3_tcpwm1_line_compl: p3_3_tcpwm1_line_compl {
742				pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_1)>;
743			};
744			/omit-if-no-ref/ p3_5_tcpwm0_line_compl: p3_5_tcpwm0_line_compl {
745				pinmux = <DT_CAT1_PINMUX(3, 5, HSIOM_SEL_ACT_0)>;
746			};
747			/omit-if-no-ref/ p3_5_tcpwm1_line_compl: p3_5_tcpwm1_line_compl {
748				pinmux = <DT_CAT1_PINMUX(3, 5, HSIOM_SEL_ACT_1)>;
749			};
750			/omit-if-no-ref/ p4_1_tcpwm0_line_compl: p4_1_tcpwm0_line_compl {
751				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_0)>;
752			};
753			/omit-if-no-ref/ p4_1_tcpwm1_line_compl: p4_1_tcpwm1_line_compl {
754				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_1)>;
755			};
756			/omit-if-no-ref/ p5_1_tcpwm0_line_compl: p5_1_tcpwm0_line_compl {
757				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_0)>;
758			};
759			/omit-if-no-ref/ p5_1_tcpwm1_line_compl: p5_1_tcpwm1_line_compl {
760				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_1)>;
761			};
762			/omit-if-no-ref/ p5_3_tcpwm0_line_compl: p5_3_tcpwm0_line_compl {
763				pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_0)>;
764			};
765			/omit-if-no-ref/ p5_3_tcpwm1_line_compl: p5_3_tcpwm1_line_compl {
766				pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_1)>;
767			};
768			/omit-if-no-ref/ p5_5_tcpwm0_line_compl: p5_5_tcpwm0_line_compl {
769				pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_0)>;
770			};
771			/omit-if-no-ref/ p5_5_tcpwm1_line_compl: p5_5_tcpwm1_line_compl {
772				pinmux = <DT_CAT1_PINMUX(5, 5, HSIOM_SEL_ACT_1)>;
773			};
774			/omit-if-no-ref/ p5_7_tcpwm0_line_compl: p5_7_tcpwm0_line_compl {
775				pinmux = <DT_CAT1_PINMUX(5, 7, HSIOM_SEL_ACT_0)>;
776			};
777			/omit-if-no-ref/ p5_7_tcpwm1_line_compl: p5_7_tcpwm1_line_compl {
778				pinmux = <DT_CAT1_PINMUX(5, 7, HSIOM_SEL_ACT_1)>;
779			};
780			/omit-if-no-ref/ p6_1_tcpwm0_line_compl: p6_1_tcpwm0_line_compl {
781				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_0)>;
782			};
783			/omit-if-no-ref/ p6_1_tcpwm1_line_compl: p6_1_tcpwm1_line_compl {
784				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_1)>;
785			};
786			/omit-if-no-ref/ p6_3_tcpwm0_line_compl: p6_3_tcpwm0_line_compl {
787				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_0)>;
788			};
789			/omit-if-no-ref/ p6_3_tcpwm1_line_compl: p6_3_tcpwm1_line_compl {
790				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_1)>;
791			};
792			/omit-if-no-ref/ p6_5_tcpwm0_line_compl: p6_5_tcpwm0_line_compl {
793				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_0)>;
794			};
795			/omit-if-no-ref/ p6_5_tcpwm1_line_compl: p6_5_tcpwm1_line_compl {
796				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_1)>;
797			};
798			/omit-if-no-ref/ p6_7_tcpwm0_line_compl: p6_7_tcpwm0_line_compl {
799				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_0)>;
800			};
801			/omit-if-no-ref/ p6_7_tcpwm1_line_compl: p6_7_tcpwm1_line_compl {
802				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_1)>;
803			};
804			/omit-if-no-ref/ p7_1_tcpwm0_line_compl: p7_1_tcpwm0_line_compl {
805				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_0)>;
806			};
807			/omit-if-no-ref/ p7_1_tcpwm1_line_compl: p7_1_tcpwm1_line_compl {
808				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_1)>;
809			};
810			/omit-if-no-ref/ p7_3_tcpwm0_line_compl: p7_3_tcpwm0_line_compl {
811				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_0)>;
812			};
813			/omit-if-no-ref/ p7_3_tcpwm1_line_compl: p7_3_tcpwm1_line_compl {
814				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_1)>;
815			};
816			/omit-if-no-ref/ p7_5_tcpwm0_line_compl: p7_5_tcpwm0_line_compl {
817				pinmux = <DT_CAT1_PINMUX(7, 5, HSIOM_SEL_ACT_0)>;
818			};
819			/omit-if-no-ref/ p7_5_tcpwm1_line_compl: p7_5_tcpwm1_line_compl {
820				pinmux = <DT_CAT1_PINMUX(7, 5, HSIOM_SEL_ACT_1)>;
821			};
822			/omit-if-no-ref/ p7_7_tcpwm0_line_compl: p7_7_tcpwm0_line_compl {
823				pinmux = <DT_CAT1_PINMUX(7, 7, HSIOM_SEL_ACT_0)>;
824			};
825			/omit-if-no-ref/ p7_7_tcpwm1_line_compl: p7_7_tcpwm1_line_compl {
826				pinmux = <DT_CAT1_PINMUX(7, 7, HSIOM_SEL_ACT_1)>;
827			};
828			/omit-if-no-ref/ p8_1_tcpwm0_line_compl: p8_1_tcpwm0_line_compl {
829				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_0)>;
830			};
831			/omit-if-no-ref/ p8_1_tcpwm1_line_compl: p8_1_tcpwm1_line_compl {
832				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_1)>;
833			};
834			/omit-if-no-ref/ p8_3_tcpwm0_line_compl: p8_3_tcpwm0_line_compl {
835				pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_0)>;
836			};
837			/omit-if-no-ref/ p8_3_tcpwm1_line_compl: p8_3_tcpwm1_line_compl {
838				pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_1)>;
839			};
840			/omit-if-no-ref/ p8_5_tcpwm0_line_compl: p8_5_tcpwm0_line_compl {
841				pinmux = <DT_CAT1_PINMUX(8, 5, HSIOM_SEL_ACT_0)>;
842			};
843			/omit-if-no-ref/ p8_5_tcpwm1_line_compl: p8_5_tcpwm1_line_compl {
844				pinmux = <DT_CAT1_PINMUX(8, 5, HSIOM_SEL_ACT_1)>;
845			};
846			/omit-if-no-ref/ p8_7_tcpwm0_line_compl: p8_7_tcpwm0_line_compl {
847				pinmux = <DT_CAT1_PINMUX(8, 7, HSIOM_SEL_ACT_0)>;
848			};
849			/omit-if-no-ref/ p8_7_tcpwm1_line_compl: p8_7_tcpwm1_line_compl {
850				pinmux = <DT_CAT1_PINMUX(8, 7, HSIOM_SEL_ACT_1)>;
851			};
852			/omit-if-no-ref/ p9_1_tcpwm0_line_compl: p9_1_tcpwm0_line_compl {
853				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_0)>;
854			};
855			/omit-if-no-ref/ p9_1_tcpwm1_line_compl: p9_1_tcpwm1_line_compl {
856				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_1)>;
857			};
858			/omit-if-no-ref/ p9_3_tcpwm0_line_compl: p9_3_tcpwm0_line_compl {
859				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_0)>;
860			};
861			/omit-if-no-ref/ p9_3_tcpwm1_line_compl: p9_3_tcpwm1_line_compl {
862				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_1)>;
863			};
864			/omit-if-no-ref/ p9_5_tcpwm0_line_compl: p9_5_tcpwm0_line_compl {
865				pinmux = <DT_CAT1_PINMUX(9, 5, HSIOM_SEL_ACT_0)>;
866			};
867			/omit-if-no-ref/ p9_5_tcpwm1_line_compl: p9_5_tcpwm1_line_compl {
868				pinmux = <DT_CAT1_PINMUX(9, 5, HSIOM_SEL_ACT_1)>;
869			};
870			/omit-if-no-ref/ p9_7_tcpwm0_line_compl: p9_7_tcpwm0_line_compl {
871				pinmux = <DT_CAT1_PINMUX(9, 7, HSIOM_SEL_ACT_0)>;
872			};
873			/omit-if-no-ref/ p9_7_tcpwm1_line_compl: p9_7_tcpwm1_line_compl {
874				pinmux = <DT_CAT1_PINMUX(9, 7, HSIOM_SEL_ACT_1)>;
875			};
876			/omit-if-no-ref/ p10_1_tcpwm0_line_compl: p10_1_tcpwm0_line_compl {
877				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_0)>;
878			};
879			/omit-if-no-ref/ p10_1_tcpwm1_line_compl: p10_1_tcpwm1_line_compl {
880				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_1)>;
881			};
882			/omit-if-no-ref/ p10_3_tcpwm0_line_compl: p10_3_tcpwm0_line_compl {
883				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_0)>;
884			};
885			/omit-if-no-ref/ p10_3_tcpwm1_line_compl: p10_3_tcpwm1_line_compl {
886				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_1)>;
887			};
888			/omit-if-no-ref/ p10_5_tcpwm0_line_compl: p10_5_tcpwm0_line_compl {
889				pinmux = <DT_CAT1_PINMUX(10, 5, HSIOM_SEL_ACT_0)>;
890			};
891			/omit-if-no-ref/ p10_5_tcpwm1_line_compl: p10_5_tcpwm1_line_compl {
892				pinmux = <DT_CAT1_PINMUX(10, 5, HSIOM_SEL_ACT_1)>;
893			};
894			/omit-if-no-ref/ p10_7_tcpwm0_line_compl: p10_7_tcpwm0_line_compl {
895				pinmux = <DT_CAT1_PINMUX(10, 7, HSIOM_SEL_ACT_0)>;
896			};
897			/omit-if-no-ref/ p10_7_tcpwm1_line_compl: p10_7_tcpwm1_line_compl {
898				pinmux = <DT_CAT1_PINMUX(10, 7, HSIOM_SEL_ACT_1)>;
899			};
900			/omit-if-no-ref/ p11_1_tcpwm0_line_compl: p11_1_tcpwm0_line_compl {
901				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_0)>;
902			};
903			/omit-if-no-ref/ p11_1_tcpwm1_line_compl: p11_1_tcpwm1_line_compl {
904				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_1)>;
905			};
906			/omit-if-no-ref/ p11_3_tcpwm0_line_compl: p11_3_tcpwm0_line_compl {
907				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_0)>;
908			};
909			/omit-if-no-ref/ p11_3_tcpwm1_line_compl: p11_3_tcpwm1_line_compl {
910				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_1)>;
911			};
912			/omit-if-no-ref/ p11_5_tcpwm0_line_compl: p11_5_tcpwm0_line_compl {
913				pinmux = <DT_CAT1_PINMUX(11, 5, HSIOM_SEL_ACT_0)>;
914			};
915			/omit-if-no-ref/ p11_5_tcpwm1_line_compl: p11_5_tcpwm1_line_compl {
916				pinmux = <DT_CAT1_PINMUX(11, 5, HSIOM_SEL_ACT_1)>;
917			};
918			/omit-if-no-ref/ p12_1_tcpwm0_line_compl: p12_1_tcpwm0_line_compl {
919				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_0)>;
920			};
921			/omit-if-no-ref/ p12_1_tcpwm1_line_compl: p12_1_tcpwm1_line_compl {
922				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_1)>;
923			};
924			/omit-if-no-ref/ p12_3_tcpwm0_line_compl: p12_3_tcpwm0_line_compl {
925				pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_0)>;
926			};
927			/omit-if-no-ref/ p12_3_tcpwm1_line_compl: p12_3_tcpwm1_line_compl {
928				pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_1)>;
929			};
930			/omit-if-no-ref/ p12_5_tcpwm0_line_compl: p12_5_tcpwm0_line_compl {
931				pinmux = <DT_CAT1_PINMUX(12, 5, HSIOM_SEL_ACT_0)>;
932			};
933			/omit-if-no-ref/ p12_5_tcpwm1_line_compl: p12_5_tcpwm1_line_compl {
934				pinmux = <DT_CAT1_PINMUX(12, 5, HSIOM_SEL_ACT_1)>;
935			};
936			/omit-if-no-ref/ p12_7_tcpwm0_line_compl: p12_7_tcpwm0_line_compl {
937				pinmux = <DT_CAT1_PINMUX(12, 7, HSIOM_SEL_ACT_0)>;
938			};
939			/omit-if-no-ref/ p12_7_tcpwm1_line_compl: p12_7_tcpwm1_line_compl {
940				pinmux = <DT_CAT1_PINMUX(12, 7, HSIOM_SEL_ACT_1)>;
941			};
942			/omit-if-no-ref/ p13_1_tcpwm0_line_compl: p13_1_tcpwm0_line_compl {
943				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_0)>;
944			};
945			/omit-if-no-ref/ p13_1_tcpwm1_line_compl: p13_1_tcpwm1_line_compl {
946				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_1)>;
947			};
948			/omit-if-no-ref/ p13_3_tcpwm0_line_compl: p13_3_tcpwm0_line_compl {
949				pinmux = <DT_CAT1_PINMUX(13, 3, HSIOM_SEL_ACT_0)>;
950			};
951			/omit-if-no-ref/ p13_3_tcpwm1_line_compl: p13_3_tcpwm1_line_compl {
952				pinmux = <DT_CAT1_PINMUX(13, 3, HSIOM_SEL_ACT_1)>;
953			};
954			/omit-if-no-ref/ p13_5_tcpwm0_line_compl: p13_5_tcpwm0_line_compl {
955				pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_0)>;
956			};
957			/omit-if-no-ref/ p13_5_tcpwm1_line_compl: p13_5_tcpwm1_line_compl {
958				pinmux = <DT_CAT1_PINMUX(13, 5, HSIOM_SEL_ACT_1)>;
959			};
960			/omit-if-no-ref/ p13_7_tcpwm0_line_compl: p13_7_tcpwm0_line_compl {
961				pinmux = <DT_CAT1_PINMUX(13, 7, HSIOM_SEL_ACT_0)>;
962			};
963			/omit-if-no-ref/ p13_7_tcpwm1_line_compl: p13_7_tcpwm1_line_compl {
964				pinmux = <DT_CAT1_PINMUX(13, 7, HSIOM_SEL_ACT_1)>;
965			};
966
967		};
968	};
969};
970