1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
10#include "psoc6_01.dtsi"
11
12/ {
13	soc {
14
15		pinctrl: pinctrl@40310000 {
16			/* scb_i2c_scl */
17			/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
18				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_7)>;
19			};
20			/omit-if-no-ref/ p1_0_scb7_i2c_scl: p1_0_scb7_i2c_scl {
21				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_7)>;
22			};
23			/omit-if-no-ref/ p2_0_scb1_i2c_scl: p2_0_scb1_i2c_scl {
24				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_7)>;
25			};
26			/omit-if-no-ref/ p3_0_scb2_i2c_scl: p3_0_scb2_i2c_scl {
27				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_7)>;
28			};
29			/omit-if-no-ref/ p4_0_scb7_i2c_scl: p4_0_scb7_i2c_scl {
30				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_7)>;
31			};
32			/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
33				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
34			};
35			/omit-if-no-ref/ p6_0_scb3_i2c_scl: p6_0_scb3_i2c_scl {
36				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_7)>;
37			};
38			/omit-if-no-ref/ p6_0_scb8_i2c_scl: p6_0_scb8_i2c_scl {
39				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_DS_2)>;
40			};
41			/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
42				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>;
43			};
44			/omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl {
45				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
46			};
47			/omit-if-no-ref/ p7_0_scb4_i2c_scl: p7_0_scb4_i2c_scl {
48				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_7)>;
49			};
50			/omit-if-no-ref/ p8_0_scb4_i2c_scl: p8_0_scb4_i2c_scl {
51				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_7)>;
52			};
53			/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
54				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
55			};
56			/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
57				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
58			};
59			/omit-if-no-ref/ p11_0_scb5_i2c_scl: p11_0_scb5_i2c_scl {
60				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_7)>;
61			};
62			/omit-if-no-ref/ p12_0_scb6_i2c_scl: p12_0_scb6_i2c_scl {
63				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_7)>;
64			};
65			/omit-if-no-ref/ p13_0_scb6_i2c_scl: p13_0_scb6_i2c_scl {
66				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_7)>;
67			};
68
69			/* scb_i2c_sda */
70			/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
71				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_7)>;
72			};
73			/omit-if-no-ref/ p1_1_scb7_i2c_sda: p1_1_scb7_i2c_sda {
74				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_7)>;
75			};
76			/omit-if-no-ref/ p2_1_scb1_i2c_sda: p2_1_scb1_i2c_sda {
77				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_7)>;
78			};
79			/omit-if-no-ref/ p3_1_scb2_i2c_sda: p3_1_scb2_i2c_sda {
80				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_7)>;
81			};
82			/omit-if-no-ref/ p4_1_scb7_i2c_sda: p4_1_scb7_i2c_sda {
83				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_7)>;
84			};
85			/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
86				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
87			};
88			/omit-if-no-ref/ p6_1_scb3_i2c_sda: p6_1_scb3_i2c_sda {
89				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_7)>;
90			};
91			/omit-if-no-ref/ p6_1_scb8_i2c_sda: p6_1_scb8_i2c_sda {
92				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_DS_2)>;
93			};
94			/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
95				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>;
96			};
97			/omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda {
98				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
99			};
100			/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
101				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
102			};
103			/omit-if-no-ref/ p8_1_scb4_i2c_sda: p8_1_scb4_i2c_sda {
104				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_7)>;
105			};
106			/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
107				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
108			};
109			/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
110				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
111			};
112			/omit-if-no-ref/ p11_1_scb5_i2c_sda: p11_1_scb5_i2c_sda {
113				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_7)>;
114			};
115			/omit-if-no-ref/ p12_1_scb6_i2c_sda: p12_1_scb6_i2c_sda {
116				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_7)>;
117			};
118			/omit-if-no-ref/ p13_1_scb6_i2c_sda: p13_1_scb6_i2c_sda {
119				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_7)>;
120			};
121
122			/* scb_uart_cts */
123			/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
124				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
125			};
126			/omit-if-no-ref/ p1_3_scb7_uart_cts: p1_3_scb7_uart_cts {
127				pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_6)>;
128			};
129			/omit-if-no-ref/ p2_3_scb1_uart_cts: p2_3_scb1_uart_cts {
130				pinmux = <DT_CAT1_PINMUX(2, 3, HSIOM_SEL_ACT_6)>;
131			};
132			/omit-if-no-ref/ p3_3_scb2_uart_cts: p3_3_scb2_uart_cts {
133				pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>;
134			};
135			/omit-if-no-ref/ p5_3_scb5_uart_cts: p5_3_scb5_uart_cts {
136				pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_6)>;
137			};
138			/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
139				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
140			};
141			/omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts {
142				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>;
143			};
144			/omit-if-no-ref/ p7_3_scb4_uart_cts: p7_3_scb4_uart_cts {
145				pinmux = <DT_CAT1_PINMUX(7, 3, HSIOM_SEL_ACT_6)>;
146			};
147			/omit-if-no-ref/ p8_3_scb4_uart_cts: p8_3_scb4_uart_cts {
148				pinmux = <DT_CAT1_PINMUX(8, 3, HSIOM_SEL_ACT_6)>;
149			};
150			/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
151				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
152			};
153			/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
154				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
155			};
156			/omit-if-no-ref/ p11_3_scb5_uart_cts: p11_3_scb5_uart_cts {
157				pinmux = <DT_CAT1_PINMUX(11, 3, HSIOM_SEL_ACT_6)>;
158			};
159			/omit-if-no-ref/ p12_3_scb6_uart_cts: p12_3_scb6_uart_cts {
160				pinmux = <DT_CAT1_PINMUX(12, 3, HSIOM_SEL_ACT_6)>;
161			};
162			/omit-if-no-ref/ p13_3_scb6_uart_cts: p13_3_scb6_uart_cts {
163				pinmux = <DT_CAT1_PINMUX(13, 3, HSIOM_SEL_ACT_6)>;
164			};
165
166			/* scb_uart_rts */
167			/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
168				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
169			};
170			/omit-if-no-ref/ p1_2_scb7_uart_rts: p1_2_scb7_uart_rts {
171				pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_6)>;
172			};
173			/omit-if-no-ref/ p2_2_scb1_uart_rts: p2_2_scb1_uart_rts {
174				pinmux = <DT_CAT1_PINMUX(2, 2, HSIOM_SEL_ACT_6)>;
175			};
176			/omit-if-no-ref/ p3_2_scb2_uart_rts: p3_2_scb2_uart_rts {
177				pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_6)>;
178			};
179			/omit-if-no-ref/ p5_2_scb5_uart_rts: p5_2_scb5_uart_rts {
180				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_6)>;
181			};
182			/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
183				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
184			};
185			/omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts {
186				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>;
187			};
188			/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
189				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
190			};
191			/omit-if-no-ref/ p8_2_scb4_uart_rts: p8_2_scb4_uart_rts {
192				pinmux = <DT_CAT1_PINMUX(8, 2, HSIOM_SEL_ACT_6)>;
193			};
194			/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
195				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
196			};
197			/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
198				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
199			};
200			/omit-if-no-ref/ p11_2_scb5_uart_rts: p11_2_scb5_uart_rts {
201				pinmux = <DT_CAT1_PINMUX(11, 2, HSIOM_SEL_ACT_6)>;
202			};
203			/omit-if-no-ref/ p12_2_scb6_uart_rts: p12_2_scb6_uart_rts {
204				pinmux = <DT_CAT1_PINMUX(12, 2, HSIOM_SEL_ACT_6)>;
205			};
206			/omit-if-no-ref/ p13_2_scb6_uart_rts: p13_2_scb6_uart_rts {
207				pinmux = <DT_CAT1_PINMUX(13, 2, HSIOM_SEL_ACT_6)>;
208			};
209
210			/* scb_uart_rx */
211			/omit-if-no-ref/ p0_2_scb0_uart_rx: p0_2_scb0_uart_rx {
212				pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_ACT_6)>;
213			};
214			/omit-if-no-ref/ p1_0_scb7_uart_rx: p1_0_scb7_uart_rx {
215				pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
216			};
217			/omit-if-no-ref/ p2_0_scb1_uart_rx: p2_0_scb1_uart_rx {
218				pinmux = <DT_CAT1_PINMUX(2, 0, HSIOM_SEL_ACT_6)>;
219			};
220			/omit-if-no-ref/ p3_0_scb2_uart_rx: p3_0_scb2_uart_rx {
221				pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
222			};
223			/omit-if-no-ref/ p4_0_scb7_uart_rx: p4_0_scb7_uart_rx {
224				pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_6)>;
225			};
226			/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
227				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
228			};
229			/omit-if-no-ref/ p6_0_scb3_uart_rx: p6_0_scb3_uart_rx {
230				pinmux = <DT_CAT1_PINMUX(6, 0, HSIOM_SEL_ACT_6)>;
231			};
232			/omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx {
233				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>;
234			};
235			/omit-if-no-ref/ p7_0_scb4_uart_rx: p7_0_scb4_uart_rx {
236				pinmux = <DT_CAT1_PINMUX(7, 0, HSIOM_SEL_ACT_6)>;
237			};
238			/omit-if-no-ref/ p8_0_scb4_uart_rx: p8_0_scb4_uart_rx {
239				pinmux = <DT_CAT1_PINMUX(8, 0, HSIOM_SEL_ACT_6)>;
240			};
241			/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
242				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
243			};
244			/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
245				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
246			};
247			/omit-if-no-ref/ p11_0_scb5_uart_rx: p11_0_scb5_uart_rx {
248				pinmux = <DT_CAT1_PINMUX(11, 0, HSIOM_SEL_ACT_6)>;
249			};
250			/omit-if-no-ref/ p12_0_scb6_uart_rx: p12_0_scb6_uart_rx {
251				pinmux = <DT_CAT1_PINMUX(12, 0, HSIOM_SEL_ACT_6)>;
252			};
253			/omit-if-no-ref/ p13_0_scb6_uart_rx: p13_0_scb6_uart_rx {
254				pinmux = <DT_CAT1_PINMUX(13, 0, HSIOM_SEL_ACT_6)>;
255			};
256
257			/* scb_uart_tx */
258			/omit-if-no-ref/ p0_3_scb0_uart_tx: p0_3_scb0_uart_tx {
259				pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_6)>;
260			};
261			/omit-if-no-ref/ p1_1_scb7_uart_tx: p1_1_scb7_uart_tx {
262				pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
263			};
264			/omit-if-no-ref/ p2_1_scb1_uart_tx: p2_1_scb1_uart_tx {
265				pinmux = <DT_CAT1_PINMUX(2, 1, HSIOM_SEL_ACT_6)>;
266			};
267			/omit-if-no-ref/ p3_1_scb2_uart_tx: p3_1_scb2_uart_tx {
268				pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
269			};
270			/omit-if-no-ref/ p4_1_scb7_uart_tx: p4_1_scb7_uart_tx {
271				pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_ACT_6)>;
272			};
273			/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
274				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
275			};
276			/omit-if-no-ref/ p6_1_scb3_uart_tx: p6_1_scb3_uart_tx {
277				pinmux = <DT_CAT1_PINMUX(6, 1, HSIOM_SEL_ACT_6)>;
278			};
279			/omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx {
280				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>;
281			};
282			/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
283				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
284			};
285			/omit-if-no-ref/ p8_1_scb4_uart_tx: p8_1_scb4_uart_tx {
286				pinmux = <DT_CAT1_PINMUX(8, 1, HSIOM_SEL_ACT_6)>;
287			};
288			/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
289				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
290			};
291			/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
292				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
293			};
294			/omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx {
295				pinmux = <DT_CAT1_PINMUX(11, 1, HSIOM_SEL_ACT_6)>;
296			};
297			/omit-if-no-ref/ p12_1_scb6_uart_tx: p12_1_scb6_uart_tx {
298				pinmux = <DT_CAT1_PINMUX(12, 1, HSIOM_SEL_ACT_6)>;
299			};
300			/omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx {
301				pinmux = <DT_CAT1_PINMUX(13, 1, HSIOM_SEL_ACT_6)>;
302			};
303
304		};
305	};
306};
307