1 /*
2 * Copyright (c) 2018 Henrik Brix Andersen <henrik@brixandersen.dk>
3 * Copyright (c) 2017 Google LLC.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT atmel_sam0_watchdog
9
10 #include <soc.h>
11 #include <zephyr/drivers/watchdog.h>
12
13 #define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
14 #include <zephyr/logging/log.h>
15 #include <zephyr/irq.h>
16 LOG_MODULE_REGISTER(wdt_sam0);
17
18 #define WDT_REGS ((Wdt *)DT_INST_REG_ADDR(0))
19
20 #ifndef WDT_CONFIG_PER_8_Val
21 #define WDT_CONFIG_PER_8_Val WDT_CONFIG_PER_CYC8_Val
22 #endif
23 #ifndef WDT_CONFIG_PER_8K_Val
24 #define WDT_CONFIG_PER_8K_Val WDT_CONFIG_PER_CYC8192_Val
25 #endif
26 #ifndef WDT_CONFIG_PER_16K_Val
27 #define WDT_CONFIG_PER_16K_Val WDT_CONFIG_PER_CYC16384_Val
28 #endif
29
30 /* syncbusy check is different for SAM D/E */
31 #ifdef WDT_STATUS_SYNCBUSY
32 #define WDT_SYNCBUSY WDT_REGS->STATUS.bit.SYNCBUSY
33 #else
34 #define WDT_SYNCBUSY WDT_REGS->SYNCBUSY.reg
35 #endif
36
37 struct wdt_sam0_dev_data {
38 wdt_callback_t cb;
39 bool timeout_valid;
40 };
41
42 static struct wdt_sam0_dev_data wdt_sam0_data = { 0 };
43
wdt_sam0_wait_synchronization(void)44 static void wdt_sam0_wait_synchronization(void)
45 {
46 while (WDT_SYNCBUSY) {
47 /* wait for SYNCBUSY */
48 }
49 }
50
wdt_sam0_set_enable(bool on)51 static inline void wdt_sam0_set_enable(bool on)
52 {
53 #ifdef WDT_CTRLA_ENABLE
54 WDT_REGS->CTRLA.bit.ENABLE = on;
55 #else
56 WDT_REGS->CTRL.bit.ENABLE = on;
57 #endif
58 }
59
wdt_sam0_is_enabled(void)60 static inline bool wdt_sam0_is_enabled(void)
61 {
62 #ifdef WDT_CTRLA_ENABLE
63 return WDT_REGS->CTRLA.bit.ENABLE;
64 #else
65 return WDT_REGS->CTRL.bit.ENABLE;
66 #endif
67 }
68
wdt_sam0_timeout_to_wdt_period(uint32_t timeout_ms)69 static uint32_t wdt_sam0_timeout_to_wdt_period(uint32_t timeout_ms)
70 {
71 uint32_t next_pow2;
72 uint32_t cycles;
73
74 /* Calculate number of clock cycles @ 1.024 kHz input clock */
75 cycles = (timeout_ms * 1024U) / 1000;
76
77 /* Minimum wdt period is 8 clock cycles (register value 0) */
78 if (cycles <= 8U) {
79 return 0;
80 }
81
82 /* Round up to next pow2 and calculate the register value */
83 next_pow2 = (1ULL << 32) >> __builtin_clz(cycles - 1);
84 return find_msb_set(next_pow2 >> 4);
85 }
86
wdt_sam0_isr(const struct device * dev)87 static void wdt_sam0_isr(const struct device *dev)
88 {
89 struct wdt_sam0_dev_data *data = dev->data;
90
91 WDT_REGS->INTFLAG.reg = WDT_INTFLAG_EW;
92
93 if (data->cb != NULL) {
94 data->cb(dev, 0);
95 }
96 }
97
wdt_sam0_setup(const struct device * dev,uint8_t options)98 static int wdt_sam0_setup(const struct device *dev, uint8_t options)
99 {
100 struct wdt_sam0_dev_data *data = dev->data;
101
102 if (wdt_sam0_is_enabled()) {
103 LOG_ERR("Watchdog already setup");
104 return -EBUSY;
105 }
106
107 if (!data->timeout_valid) {
108 LOG_ERR("No valid timeout installed");
109 return -EINVAL;
110 }
111
112 if (options & WDT_OPT_PAUSE_IN_SLEEP) {
113 LOG_ERR("Pause in sleep not supported");
114 return -ENOTSUP;
115 }
116
117 if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
118 LOG_ERR("Pause when halted by debugger not supported");
119 return -ENOTSUP;
120 }
121
122 /* Enable watchdog */
123 wdt_sam0_set_enable(1);
124 wdt_sam0_wait_synchronization();
125
126 return 0;
127 }
128
wdt_sam0_disable(const struct device * dev)129 static int wdt_sam0_disable(const struct device *dev)
130 {
131 if (!wdt_sam0_is_enabled()) {
132 return -EFAULT;
133 }
134
135 wdt_sam0_set_enable(0);
136 wdt_sam0_wait_synchronization();
137
138 return 0;
139 }
140
wdt_sam0_install_timeout(const struct device * dev,const struct wdt_timeout_cfg * cfg)141 static int wdt_sam0_install_timeout(const struct device *dev,
142 const struct wdt_timeout_cfg *cfg)
143 {
144 struct wdt_sam0_dev_data *data = dev->data;
145 uint32_t window, per;
146
147 /* CONFIG is enable protected, error out if already enabled */
148 if (wdt_sam0_is_enabled()) {
149 LOG_ERR("Watchdog already setup");
150 return -EBUSY;
151 }
152
153 if (cfg->flags != WDT_FLAG_RESET_SOC) {
154 LOG_ERR("Only SoC reset supported");
155 return -ENOTSUP;
156 }
157
158 if (cfg->window.max == 0) {
159 LOG_ERR("Upper limit timeout out of range");
160 return -EINVAL;
161 }
162
163 per = wdt_sam0_timeout_to_wdt_period(cfg->window.max);
164 if (per > WDT_CONFIG_PER_16K_Val) {
165 LOG_ERR("Upper limit timeout out of range");
166 goto timeout_invalid;
167 }
168
169 if (cfg->window.min) {
170 /* Window mode */
171 window = wdt_sam0_timeout_to_wdt_period(cfg->window.min);
172 if (window > WDT_CONFIG_PER_8K_Val) {
173 LOG_ERR("Lower limit timeout out of range");
174 goto timeout_invalid;
175 }
176 if (per <= window) {
177 /* Ensure we have a window */
178 per = window + 1;
179 }
180 #ifdef WDT_CTRLA_WEN
181 WDT_REGS->CTRLA.bit.WEN = 1;
182 #else
183 WDT_REGS->CTRL.bit.WEN = 1;
184 #endif
185 wdt_sam0_wait_synchronization();
186 } else {
187 /* Normal mode */
188 if (cfg->callback) {
189 if (per == WDT_CONFIG_PER_8_Val) {
190 /* Ensure we have time for the early warning */
191 per += 1U;
192 }
193 WDT_REGS->EWCTRL.bit.EWOFFSET = per - 1U;
194 }
195 window = WDT_CONFIG_PER_8_Val;
196 #ifdef WDT_CTRLA_WEN
197 WDT_REGS->CTRLA.bit.WEN = 0;
198 #else
199 WDT_REGS->CTRL.bit.WEN = 0;
200 #endif
201 wdt_sam0_wait_synchronization();
202 }
203
204 WDT_REGS->CONFIG.reg = WDT_CONFIG_WINDOW(window) | WDT_CONFIG_PER(per);
205 wdt_sam0_wait_synchronization();
206
207 /* Only enable IRQ if a callback was provided */
208 data->cb = cfg->callback;
209 if (data->cb) {
210 WDT_REGS->INTENSET.reg = WDT_INTENSET_EW;
211 } else {
212 WDT_REGS->INTENCLR.reg = WDT_INTENCLR_EW;
213 WDT_REGS->INTFLAG.reg = WDT_INTFLAG_EW;
214 }
215
216 data->timeout_valid = true;
217
218 return 0;
219
220 timeout_invalid:
221 data->timeout_valid = false;
222 data->cb = NULL;
223
224 return -EINVAL;
225 }
226
wdt_sam0_feed(const struct device * dev,int channel_id)227 static int wdt_sam0_feed(const struct device *dev, int channel_id)
228 {
229 struct wdt_sam0_dev_data *data = dev->data;
230
231 if (!data->timeout_valid) {
232 LOG_ERR("No valid timeout installed");
233 return -EINVAL;
234 }
235
236 if (WDT_SYNCBUSY) {
237 return -EAGAIN;
238 }
239
240 WDT_REGS->CLEAR.reg = WDT_CLEAR_CLEAR_KEY_Val;
241
242 return 0;
243 }
244
245 static const struct wdt_driver_api wdt_sam0_api = {
246 .setup = wdt_sam0_setup,
247 .disable = wdt_sam0_disable,
248 .install_timeout = wdt_sam0_install_timeout,
249 .feed = wdt_sam0_feed,
250 };
251
wdt_sam0_init(const struct device * dev)252 static int wdt_sam0_init(const struct device *dev)
253 {
254 #ifdef CONFIG_WDT_DISABLE_AT_BOOT
255 /* Ignore any errors */
256 wdt_sam0_disable(dev);
257 #endif
258 /* Enable APB clock */
259 #ifdef MCLK
260 MCLK->APBAMASK.bit.WDT_ = 1;
261
262 /* watchdog clock is fed by OSCULP32K */
263 #else
264 PM->APBAMASK.bit.WDT_ = 1;
265
266 /* Connect to GCLK2 (~1.024 kHz) */
267 GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_WDT
268 | GCLK_CLKCTRL_GEN_GCLK2
269 | GCLK_CLKCTRL_CLKEN;
270 #endif
271
272 IRQ_CONNECT(DT_INST_IRQN(0),
273 DT_INST_IRQ(0, priority), wdt_sam0_isr,
274 DEVICE_DT_INST_GET(0), 0);
275 irq_enable(DT_INST_IRQN(0));
276
277 return 0;
278 }
279
280 static struct wdt_sam0_dev_data wdt_sam0_data;
281
282 DEVICE_DT_INST_DEFINE(0, wdt_sam0_init, NULL,
283 &wdt_sam0_data, NULL, PRE_KERNEL_1,
284 CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_sam0_api);
285
