1 /*
2 * Copyright (c) 2021 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ovti_ov2640
8 #include <zephyr/kernel.h>
9 #include <zephyr/device.h>
10
11 #include <zephyr/drivers/video.h>
12 #include <zephyr/drivers/i2c.h>
13 #include <zephyr/drivers/gpio.h>
14
15 #define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL
16 #include <zephyr/logging/log.h>
17 LOG_MODULE_REGISTER(ov2640);
18
19 /* DSP register bank FF=0x00*/
20 #define QS 0x44
21 #define HSIZE 0x51
22 #define VSIZE 0x52
23 #define XOFFL 0x53
24 #define YOFFL 0x54
25 #define VHYX 0x55
26 #define TEST 0x57
27 #define ZMOW 0x5A
28 #define ZMOH 0x5B
29 #define ZMHH 0x5C
30 #define BPADDR 0x7C
31 #define BPDATA 0x7D
32 #define SIZEL 0x8C
33 #define HSIZE8 0xC0
34 #define VSIZE8 0xC1
35 #define CTRL1 0xC3
36
37 #define CTRLI 0x50
38 #define CTRLI_LP_DP 0x80
39
40 #define CTRL0 0xC2
41 #define CTRL0_YUV422 0x08
42 #define CTRL0_YUV_EN 0x04
43 #define CTRL0_RGB_EN 0x02
44
45 #define CTRL2 0x86
46 #define CTRL2_DCW_EN 0x20
47 #define CTRL2_SDE_EN 0x10
48 #define CTRL2_UV_ADJ_EN 0x08
49 #define CTRL2_UV_AVG_EN 0x04
50 #define CTRL2_CMX_EN 0x01
51
52 #define CTRL3 0x87
53 #define CTRL3_BPC_EN 0x80
54 #define CTRL3_WPC_EN 0x40
55 #define R_DVP_SP 0xD3
56 #define R_DVP_SP_AUTO_MODE 0x80
57
58 #define R_BYPASS 0x05
59 #define R_BYPASS_DSP_EN 0x00
60 #define R_BYPASS_DSP_BYPAS 0x01
61
62 #define IMAGE_MODE 0xDA
63 #define IMAGE_MODE_JPEG_EN 0x10
64 #define IMAGE_MODE_RGB565 0x08
65
66 #define RESET 0xE0
67 #define RESET_JPEG 0x10
68 #define RESET_DVP 0x04
69
70 #define MC_BIST 0xF9
71 #define MC_BIST_RESET 0x80
72 #define MC_BIST_BOOT_ROM_SEL 0x40
73
74 #define BANK_SEL 0xFF
75 #define BANK_SEL_DSP 0x00
76 #define BANK_SEL_SENSOR 0x01
77
78 /* Sensor register bank FF=0x01*/
79 #define COM1 0x03
80 #define REG_PID 0x0A
81 #define REG_PID_VAL 0x26
82 #define REG_VER 0x0B
83 #define REG_VER_VAL 0x42
84 #define AEC 0x10
85 #define CLKRC 0x11
86 #define COM10 0x15
87 #define HSTART 0x17
88 #define HSTOP 0x18
89 #define VSTART 0x19
90 #define VSTOP 0x1A
91 #define AEW 0x24
92 #define AEB 0x25
93 #define ARCOM2 0x34
94 #define FLL 0x46
95 #define FLH 0x47
96 #define COM19 0x48
97 #define ZOOMS 0x49
98 #define BD50 0x4F
99 #define BD60 0x50
100 #define REG5D 0x5D
101 #define REG5E 0x5E
102 #define REG5F 0x5F
103 #define REG60 0x60
104 #define HISTO_LOW 0x61
105 #define HISTO_HIGH 0x62
106
107 #define REG04 0x04
108 #define REG04_DEFAULT 0x28
109 #define REG04_HFLIP_IMG 0x80
110 #define REG04_VFLIP_IMG 0x40
111 #define REG04_HREF_EN 0x08
112 #define REG04_SET(x) (REG04_DEFAULT | x)
113
114 #define COM2 0x09
115 #define COM2_OUT_DRIVE_3x 0x02
116
117 #define COM3 0x0C
118 #define COM3_DEFAULT 0x38
119 #define COM3_BAND_AUTO 0x02
120 #define COM3_BAND_SET(x) (COM3_DEFAULT | x)
121
122 #define COM7 0x12
123 #define COM7_SRST 0x80
124 #define COM7_RES_UXGA 0x00 /* UXGA */
125 #define COM7_ZOOM_EN 0x04 /* Enable Zoom */
126 #define COM7_COLOR_BAR 0x02 /* Enable Color Bar Test */
127
128 #define COM8 0x13
129 #define COM8_DEFAULT 0xC0
130 #define COM8_BNDF_EN 0x20 /* Enable Banding filter */
131 #define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
132 #define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
133 #define COM8_SET(x) (COM8_DEFAULT | x)
134
135 #define COM9 0x14 /* AGC gain ceiling */
136 #define COM9_DEFAULT 0x08
137 #define COM9_AGC_GAIN_8x 0x02 /* AGC: 8x */
138 #define COM9_AGC_SET(x) (COM9_DEFAULT | (x << 5))
139
140 #define COM10 0x15
141
142 #define CTRL1_AWB 0x08 /* Enable AWB */
143
144 #define VV 0x26
145 #define VV_AGC_TH_SET(h, l) ((h << 4) | (l & 0x0F))
146
147 #define REG32 0x32
148 #define REG32_UXGA 0x36
149
150 /* Configuration arrays */
151 #define SVGA_HSIZE (800)
152 #define SVGA_VSIZE (600)
153
154 #define UXGA_HSIZE (1600)
155 #define UXGA_VSIZE (1200)
156
157 struct ov2640_reg {
158 uint8_t addr;
159 uint8_t value;
160 };
161
162 static const struct ov2640_reg default_regs[] = {
163 { BANK_SEL, BANK_SEL_DSP },
164 { 0x2c, 0xff },
165 { 0x2e, 0xdf },
166 { BANK_SEL, BANK_SEL_SENSOR },
167 { 0x3c, 0x32 },
168 { CLKRC, 0x80 }, /* Set PCLK divider */
169 { COM2, COM2_OUT_DRIVE_3x }, /* Output drive x2 */
170 { REG04, REG04_SET(REG04_HREF_EN)},
171 { COM8, COM8_SET(COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN) },
172 { COM9, COM9_AGC_SET(COM9_AGC_GAIN_8x)},
173 { COM10, 0x00 }, /* Invert VSYNC */
174 { 0x2c, 0x0c },
175 { 0x33, 0x78 },
176 { 0x3a, 0x33 },
177 { 0x3b, 0xfb },
178 { 0x3e, 0x00 },
179 { 0x43, 0x11 },
180 { 0x16, 0x10 },
181 { 0x39, 0x02 },
182 { 0x35, 0x88 },
183 { 0x22, 0x0a },
184 { 0x37, 0x40 },
185 { 0x23, 0x00 },
186 { ARCOM2, 0xa0 },
187 { 0x06, 0x02 },
188 { 0x06, 0x88 },
189 { 0x07, 0xc0 },
190 { 0x0d, 0xb7 },
191 { 0x0e, 0x01 },
192 { 0x4c, 0x00 },
193 { 0x4a, 0x81 },
194 { 0x21, 0x99 },
195 { AEW, 0x40 },
196 { AEB, 0x38 },
197 /* AGC/AEC fast mode operating region */
198 { VV, VV_AGC_TH_SET(0x08, 0x02) },
199 { COM19, 0x00 }, /* Zoom control 2 LSBs */
200 { ZOOMS, 0x00 }, /* Zoom control 8 MSBs */
201 { 0x5c, 0x00 },
202 { 0x63, 0x00 },
203 { FLL, 0x00 },
204 { FLH, 0x00 },
205
206 /* Set banding filter */
207 { COM3, COM3_BAND_SET(COM3_BAND_AUTO) },
208 { REG5D, 0x55 },
209 { REG5E, 0x7d },
210 { REG5F, 0x7d },
211 { REG60, 0x55 },
212 { HISTO_LOW, 0x70 },
213 { HISTO_HIGH, 0x80 },
214 { 0x7c, 0x05 },
215 { 0x20, 0x80 },
216 { 0x28, 0x30 },
217 { 0x6c, 0x00 },
218 { 0x6d, 0x80 },
219 { 0x6e, 0x00 },
220 { 0x70, 0x02 },
221 { 0x71, 0x94 },
222 { 0x73, 0xc1 },
223 { 0x3d, 0x34 },
224 /* { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, */
225 { 0x5a, 0x57 },
226 { BD50, 0xbb },
227 { BD60, 0x9c },
228
229 { BANK_SEL, BANK_SEL_DSP },
230 { 0xe5, 0x7f },
231 { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
232 { 0x41, 0x24 },
233 { RESET, RESET_JPEG | RESET_DVP },
234 { 0x76, 0xff },
235 { 0x33, 0xa0 },
236 { 0x42, 0x20 },
237 { 0x43, 0x18 },
238 { 0x4c, 0x00 },
239 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
240 { 0x88, 0x3f },
241 { 0xd7, 0x03 },
242 { 0xd9, 0x10 },
243 { R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x2 },
244 { 0xc8, 0x08 },
245 { 0xc9, 0x80 },
246 { BPADDR, 0x00 },
247 { BPDATA, 0x00 },
248 { BPADDR, 0x03 },
249 { BPDATA, 0x48 },
250 { BPDATA, 0x48 },
251 { BPADDR, 0x08 },
252 { BPDATA, 0x20 },
253 { BPDATA, 0x10 },
254 { BPDATA, 0x0e },
255 { 0x90, 0x00 },
256 { 0x91, 0x0e },
257 { 0x91, 0x1a },
258 { 0x91, 0x31 },
259 { 0x91, 0x5a },
260 { 0x91, 0x69 },
261 { 0x91, 0x75 },
262 { 0x91, 0x7e },
263 { 0x91, 0x88 },
264 { 0x91, 0x8f },
265 { 0x91, 0x96 },
266 { 0x91, 0xa3 },
267 { 0x91, 0xaf },
268 { 0x91, 0xc4 },
269 { 0x91, 0xd7 },
270 { 0x91, 0xe8 },
271 { 0x91, 0x20 },
272 { 0x92, 0x00 },
273 { 0x93, 0x06 },
274 { 0x93, 0xe3 },
275 { 0x93, 0x03 },
276 { 0x93, 0x03 },
277 { 0x93, 0x00 },
278 { 0x93, 0x02 },
279 { 0x93, 0x00 },
280 { 0x93, 0x00 },
281 { 0x93, 0x00 },
282 { 0x93, 0x00 },
283 { 0x93, 0x00 },
284 { 0x93, 0x00 },
285 { 0x93, 0x00 },
286 { 0x96, 0x00 },
287 { 0x97, 0x08 },
288 { 0x97, 0x19 },
289 { 0x97, 0x02 },
290 { 0x97, 0x0c },
291 { 0x97, 0x24 },
292 { 0x97, 0x30 },
293 { 0x97, 0x28 },
294 { 0x97, 0x26 },
295 { 0x97, 0x02 },
296 { 0x97, 0x98 },
297 { 0x97, 0x80 },
298 { 0x97, 0x00 },
299 { 0x97, 0x00 },
300 { 0xa4, 0x00 },
301 { 0xa8, 0x00 },
302 { 0xc5, 0x11 },
303 { 0xc6, 0x51 },
304 { 0xbf, 0x80 },
305 { 0xc7, 0x10 },
306 { 0xb6, 0x66 },
307 { 0xb8, 0xA5 },
308 { 0xb7, 0x64 },
309 { 0xb9, 0x7C },
310 { 0xb3, 0xaf },
311 { 0xb4, 0x97 },
312 { 0xb5, 0xFF },
313 { 0xb0, 0xC5 },
314 { 0xb1, 0x94 },
315 { 0xb2, 0x0f },
316 { 0xc4, 0x5c },
317 { 0xa6, 0x00 },
318 { 0xa7, 0x20 },
319 { 0xa7, 0xd8 },
320 { 0xa7, 0x1b },
321 { 0xa7, 0x31 },
322 { 0xa7, 0x00 },
323 { 0xa7, 0x18 },
324 { 0xa7, 0x20 },
325 { 0xa7, 0xd8 },
326 { 0xa7, 0x19 },
327 { 0xa7, 0x31 },
328 { 0xa7, 0x00 },
329 { 0xa7, 0x18 },
330 { 0xa7, 0x20 },
331 { 0xa7, 0xd8 },
332 { 0xa7, 0x19 },
333 { 0xa7, 0x31 },
334 { 0xa7, 0x00 },
335 { 0xa7, 0x18 },
336 { 0x7f, 0x00 },
337 { 0xe5, 0x1f },
338 { 0xe1, 0x77 },
339 { 0xdd, 0x7f },
340 { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
341 { 0x00, 0x00 }
342 };
343
344 static const struct ov2640_reg uxga_regs[] = {
345 { BANK_SEL, BANK_SEL_SENSOR },
346 /* DSP input image resolution and window size control */
347 { COM7, COM7_RES_UXGA},
348 { COM1, 0x0F }, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
349 { REG32, REG32_UXGA }, /* UXGA=0x36, SVGA/CIF=0x09 */
350
351 { HSTART, 0x11 }, /* UXGA=0x11, SVGA/CIF=0x11 */
352 { HSTOP, 0x75 }, /* UXGA=0x75, SVGA/CIF=0x43 */
353
354 { VSTART, 0x01 }, /* UXGA=0x01, SVGA/CIF=0x00 */
355 { VSTOP, 0x97 }, /* UXGA=0x97, SVGA/CIF=0x4b */
356 { 0x3d, 0x34 }, /* UXGA=0x34, SVGA/CIF=0x38 */
357
358 { 0x35, 0x88 },
359 { 0x22, 0x0a },
360 { 0x37, 0x40 },
361 { 0x34, 0xa0 },
362 { 0x06, 0x02 },
363 { 0x0d, 0xb7 },
364 { 0x0e, 0x01 },
365 { 0x42, 0x83 },
366
367 /*
368 * Set DSP input image size and offset.
369 * The sensor output image can be scaled with OUTW/OUTH
370 */
371 { BANK_SEL, BANK_SEL_DSP },
372 { R_BYPASS, R_BYPASS_DSP_BYPAS },
373
374 { RESET, RESET_DVP },
375 { HSIZE8, (UXGA_HSIZE>>3)}, /* Image Horizontal Size HSIZE[10:3] */
376 { VSIZE8, (UXGA_VSIZE>>3)}, /* Image Vertical Size VSIZE[10:3] */
377
378 /* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
379 { SIZEL, ((UXGA_HSIZE>>6)&0x40) | ((UXGA_HSIZE&0x7)<<3) | (UXGA_VSIZE&0x7)},
380
381 { XOFFL, 0x00 }, /* OFFSET_X[7:0] */
382 { YOFFL, 0x00 }, /* OFFSET_Y[7:0] */
383 { HSIZE, ((UXGA_HSIZE>>2)&0xFF) }, /* H_SIZE[7:0] real/4 */
384 { VSIZE, ((UXGA_VSIZE>>2)&0xFF) }, /* V_SIZE[7:0] real/4 */
385
386 /* V_SIZE[8]/OFFSET_Y[10:8]/H_SIZE[8]/OFFSET_X[10:8] */
387 { VHYX, ((UXGA_VSIZE>>3)&0x80) | ((UXGA_HSIZE>>7)&0x08) },
388 { TEST, (UXGA_HSIZE>>4)&0x80}, /* H_SIZE[9] */
389
390 { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
391 CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
392
393 /* H_DIVIDER/V_DIVIDER */
394 { CTRLI, CTRLI_LP_DP | 0x00},
395 /* DVP prescaler */
396 { R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x04},
397
398 { R_BYPASS, R_BYPASS_DSP_EN },
399 { RESET, 0x00 },
400 {0, 0},
401 };
402
403 #define NUM_BRIGHTNESS_LEVELS (5)
404 static const uint8_t brightness_regs[NUM_BRIGHTNESS_LEVELS + 1][5] = {
405 { BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
406 { 0x00, 0x04, 0x09, 0x00, 0x00 }, /* -2 */
407 { 0x00, 0x04, 0x09, 0x10, 0x00 }, /* -1 */
408 { 0x00, 0x04, 0x09, 0x20, 0x00 }, /* 0 */
409 { 0x00, 0x04, 0x09, 0x30, 0x00 }, /* +1 */
410 { 0x00, 0x04, 0x09, 0x40, 0x00 }, /* +2 */
411 };
412
413 #define NUM_CONTRAST_LEVELS (5)
414 static const uint8_t contrast_regs[NUM_CONTRAST_LEVELS + 1][7] = {
415 { BPADDR, BPDATA, BPADDR, BPDATA, BPDATA, BPDATA, BPDATA },
416 { 0x00, 0x04, 0x07, 0x20, 0x18, 0x34, 0x06 }, /* -2 */
417 { 0x00, 0x04, 0x07, 0x20, 0x1c, 0x2a, 0x06 }, /* -1 */
418 { 0x00, 0x04, 0x07, 0x20, 0x20, 0x20, 0x06 }, /* 0 */
419 { 0x00, 0x04, 0x07, 0x20, 0x24, 0x16, 0x06 }, /* +1 */
420 { 0x00, 0x04, 0x07, 0x20, 0x28, 0x0c, 0x06 }, /* +2 */
421 };
422
423 #define NUM_SATURATION_LEVELS (5)
424 static const uint8_t saturation_regs[NUM_SATURATION_LEVELS + 1][5] = {
425 { BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
426 { 0x00, 0x02, 0x03, 0x28, 0x28 }, /* -2 */
427 { 0x00, 0x02, 0x03, 0x38, 0x38 }, /* -1 */
428 { 0x00, 0x02, 0x03, 0x48, 0x48 }, /* 0 */
429 { 0x00, 0x02, 0x03, 0x58, 0x58 }, /* +1 */
430 { 0x00, 0x02, 0x03, 0x58, 0x58 }, /* +2 */
431 };
432
433 struct ov2640_config {
434 struct i2c_dt_spec i2c;
435 #if DT_INST_NODE_HAS_PROP(0, reset_gpios)
436 struct gpio_dt_spec reset_gpio;
437 #endif
438 };
439
440 struct ov2640_data {
441 struct video_format fmt;
442 };
443
444 #define OV2640_VIDEO_FORMAT_CAP(width, height, format) \
445 { \
446 .pixelformat = (format), \
447 .width_min = (width), \
448 .width_max = (width), \
449 .height_min = (height), \
450 .height_max = (height), \
451 .width_step = 0, \
452 .height_step = 0 \
453 }
454
455 static const struct video_format_cap fmts[] = {
456 OV2640_VIDEO_FORMAT_CAP(160, 120, VIDEO_PIX_FMT_RGB565), /* QQVGA */
457 OV2640_VIDEO_FORMAT_CAP(176, 144, VIDEO_PIX_FMT_RGB565), /* QCIF */
458 OV2640_VIDEO_FORMAT_CAP(240, 160, VIDEO_PIX_FMT_RGB565), /* HQVGA */
459 OV2640_VIDEO_FORMAT_CAP(320, 240, VIDEO_PIX_FMT_RGB565), /* QVGA */
460 OV2640_VIDEO_FORMAT_CAP(352, 288, VIDEO_PIX_FMT_RGB565), /* CIF */
461 OV2640_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_RGB565), /* VGA */
462 OV2640_VIDEO_FORMAT_CAP(800, 600, VIDEO_PIX_FMT_RGB565), /* SVGA */
463 OV2640_VIDEO_FORMAT_CAP(1024, 768, VIDEO_PIX_FMT_RGB565), /* XVGA */
464 OV2640_VIDEO_FORMAT_CAP(1280, 1024, VIDEO_PIX_FMT_RGB565), /* SXGA */
465 OV2640_VIDEO_FORMAT_CAP(1600, 1200, VIDEO_PIX_FMT_RGB565), /* UXGA */
466 OV2640_VIDEO_FORMAT_CAP(160, 120, VIDEO_PIX_FMT_JPEG), /* QQVGA */
467 OV2640_VIDEO_FORMAT_CAP(176, 144, VIDEO_PIX_FMT_JPEG), /* QCIF */
468 OV2640_VIDEO_FORMAT_CAP(240, 160, VIDEO_PIX_FMT_JPEG), /* HQVGA */
469 OV2640_VIDEO_FORMAT_CAP(320, 240, VIDEO_PIX_FMT_JPEG), /* QVGA */
470 OV2640_VIDEO_FORMAT_CAP(352, 288, VIDEO_PIX_FMT_JPEG), /* CIF */
471 OV2640_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_JPEG), /* VGA */
472 OV2640_VIDEO_FORMAT_CAP(800, 600, VIDEO_PIX_FMT_JPEG), /* SVGA */
473 OV2640_VIDEO_FORMAT_CAP(1024, 768, VIDEO_PIX_FMT_JPEG), /* XVGA */
474 OV2640_VIDEO_FORMAT_CAP(1280, 1024, VIDEO_PIX_FMT_JPEG), /* SXGA */
475 OV2640_VIDEO_FORMAT_CAP(1600, 1200, VIDEO_PIX_FMT_JPEG), /* UXGA */
476 { 0 }
477 };
478
ov2640_write_reg(const struct i2c_dt_spec * spec,uint8_t reg_addr,uint8_t value)479 static int ov2640_write_reg(const struct i2c_dt_spec *spec, uint8_t reg_addr,
480 uint8_t value)
481 {
482 uint8_t tries = 3;
483
484 /**
485 * It rarely happens that the camera does not respond with ACK signal.
486 * In that case it usually responds on 2nd try but there is a 3rd one
487 * just to be sure that the connection error is not caused by driver
488 * itself.
489 */
490 while (tries--) {
491 if (!i2c_reg_write_byte_dt(spec, reg_addr, value)) {
492 return 0;
493 }
494 /* If writing failed wait 5ms before next attempt */
495 k_msleep(5);
496 }
497 LOG_ERR("failed to write 0x%x to 0x%x", value, reg_addr);
498
499 return -1;
500 }
501
ov2640_read_reg(const struct i2c_dt_spec * spec,uint8_t reg_addr)502 static int ov2640_read_reg(const struct i2c_dt_spec *spec, uint8_t reg_addr)
503 {
504 uint8_t tries = 3;
505 uint8_t value;
506
507 /**
508 * It rarely happens that the camera does not respond with ACK signal.
509 * In that case it usually responds on 2nd try but there is a 3rd one
510 * just to be sure that the connection error is not caused by driver
511 * itself.
512 */
513 while (tries--) {
514 if (!i2c_reg_read_byte_dt(spec, reg_addr, &value)) {
515 return value;
516 }
517 /* If reading failed wait 5ms before next attempt */
518 k_msleep(5);
519 }
520 LOG_ERR("failed to read 0x%x register", reg_addr);
521
522 return -1;
523 }
524
ov2640_write_all(const struct device * dev,const struct ov2640_reg * regs,uint16_t reg_num)525 static int ov2640_write_all(const struct device *dev,
526 const struct ov2640_reg *regs, uint16_t reg_num)
527 {
528 uint16_t i = 0;
529 const struct ov2640_config *cfg = dev->config;
530
531 for (i = 0; i < reg_num; i++) {
532 int err;
533
534 err = ov2640_write_reg(&cfg->i2c, regs[i].addr, regs[i].value);
535 if (err) {
536 return err;
537 }
538 }
539
540 return 0;
541 }
542
ov2640_soft_reset(const struct device * dev)543 static int ov2640_soft_reset(const struct device *dev)
544 {
545 int ret = 0;
546 const struct ov2640_config *cfg = dev->config;
547
548 /* Switch to DSP register bank */
549 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_SENSOR);
550
551 /* Initiate system reset */
552 ret |= ov2640_write_reg(&cfg->i2c, COM7, COM7_SRST);
553
554 return ret;
555 }
556
ov2640_set_level(const struct device * dev,int level,int max_level,int cols,const uint8_t regs[][cols])557 static int ov2640_set_level(const struct device *dev, int level,
558 int max_level, int cols, const uint8_t regs[][cols])
559 {
560 int ret = 0;
561 const struct ov2640_config *cfg = dev->config;
562
563 level += (max_level / 2 + 1);
564 if (level < 0 || level > max_level) {
565 return -ENOTSUP;
566 }
567
568 /* Switch to DSP register bank */
569 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_DSP);
570
571 for (int i = 0; i < (ARRAY_SIZE(regs[0]) / sizeof(regs[0][0])); i++) {
572 ret |= ov2640_write_reg(&cfg->i2c, regs[0][i], regs[level][i]);
573 }
574
575 return ret;
576 }
577
ov2640_set_brightness(const struct device * dev,int level)578 static int ov2640_set_brightness(const struct device *dev, int level)
579 {
580 int ret = 0;
581
582 ret = ov2640_set_level(dev, level, NUM_BRIGHTNESS_LEVELS,
583 ARRAY_SIZE(brightness_regs[0]), brightness_regs);
584
585 if (ret == -ENOTSUP) {
586 LOG_ERR("Brightness level %d not supported", level);
587 }
588
589 return ret;
590 }
591
ov2640_set_saturation(const struct device * dev,int level)592 static int ov2640_set_saturation(const struct device *dev, int level)
593 {
594 int ret = 0;
595
596 ret = ov2640_set_level(dev, level, NUM_SATURATION_LEVELS,
597 ARRAY_SIZE(saturation_regs[0]), saturation_regs);
598
599 if (ret == -ENOTSUP) {
600 LOG_ERR("Saturation level %d not supported", level);
601 }
602
603 return ret;
604 }
605
ov2640_set_contrast(const struct device * dev,int level)606 static int ov2640_set_contrast(const struct device *dev, int level)
607 {
608 int ret = 0;
609
610 ret = ov2640_set_level(dev, level, NUM_CONTRAST_LEVELS,
611 ARRAY_SIZE(contrast_regs[0]), contrast_regs);
612
613 if (ret == -ENOTSUP) {
614 LOG_ERR("Contrast level %d not supported", level);
615 }
616
617 return ret;
618 }
619
ov2640_set_output_format(const struct device * dev,int output_format)620 static int ov2640_set_output_format(const struct device *dev,
621 int output_format)
622 {
623 int ret = 0;
624 const struct ov2640_config *cfg = dev->config;
625
626 /* Switch to DSP register bank */
627 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_DSP);
628
629 if (output_format == VIDEO_PIX_FMT_JPEG) {
630 /* Enable JPEG compression */
631 ret |= ov2640_write_reg(&cfg->i2c, IMAGE_MODE, IMAGE_MODE_JPEG_EN);
632 } else if (output_format == VIDEO_PIX_FMT_RGB565) {
633 /* Disable JPEG compression and set output to RGB565 */
634 ret |= ov2640_write_reg(&cfg->i2c, IMAGE_MODE, IMAGE_MODE_RGB565);
635 } else {
636 LOG_ERR("Image format not supported");
637 return -ENOTSUP;
638 }
639 k_msleep(30);
640
641 return ret;
642 }
643
ov2640_set_quality(const struct device * dev,int qs)644 static int ov2640_set_quality(const struct device *dev, int qs)
645 {
646 int ret = 0;
647 const struct ov2640_config *cfg = dev->config;
648
649 /* Switch to DSP register bank */
650 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_DSP);
651
652 /* Write QS register */
653 ret |= ov2640_write_reg(&cfg->i2c, QS, qs);
654
655 return ret;
656 }
657
ov2640_set_colorbar(const struct device * dev,uint8_t enable)658 static int ov2640_set_colorbar(const struct device *dev, uint8_t enable)
659 {
660 int ret = 0;
661 const struct ov2640_config *cfg = dev->config;
662
663 uint8_t reg;
664
665 /* Switch to SENSOR register bank */
666 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_SENSOR);
667
668 /* Update COM7 to enable/disable color bar test pattern */
669 reg = ov2640_read_reg(&cfg->i2c, COM7);
670
671 if (enable) {
672 reg |= COM7_COLOR_BAR;
673 } else {
674 reg &= ~COM7_COLOR_BAR;
675 }
676
677 ret |= ov2640_write_reg(&cfg->i2c, COM7, reg);
678
679 return ret;
680 }
681
ov2640_set_white_bal(const struct device * dev,int enable)682 static int ov2640_set_white_bal(const struct device *dev, int enable)
683 {
684 int ret = 0;
685 const struct ov2640_config *cfg = dev->config;
686
687 uint8_t reg;
688
689 /* Switch to SENSOR register bank */
690 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_SENSOR);
691
692 /* Update CTRL1 to enable/disable automatic white balance*/
693 reg = ov2640_read_reg(&cfg->i2c, CTRL1);
694
695 if (enable) {
696 reg |= CTRL1_AWB;
697 } else {
698 reg &= ~CTRL1_AWB;
699 }
700
701 ret |= ov2640_write_reg(&cfg->i2c, CTRL1, reg);
702
703 return ret;
704 }
705
ov2640_set_gain_ctrl(const struct device * dev,int enable)706 static int ov2640_set_gain_ctrl(const struct device *dev, int enable)
707 {
708 int ret = 0;
709 const struct ov2640_config *cfg = dev->config;
710
711 uint8_t reg;
712
713 /* Switch to SENSOR register bank */
714 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_SENSOR);
715
716 /* Update COM8 to enable/disable automatic gain control */
717 reg = ov2640_read_reg(&cfg->i2c, COM8);
718
719 if (enable) {
720 reg |= COM8_AGC_EN;
721 } else {
722 reg &= ~COM8_AGC_EN;
723 }
724
725 ret |= ov2640_write_reg(&cfg->i2c, COM8, reg);
726
727 return ret;
728 }
729
ov2640_set_exposure_ctrl(const struct device * dev,int enable)730 static int ov2640_set_exposure_ctrl(const struct device *dev, int enable)
731 {
732 int ret = 0;
733 const struct ov2640_config *cfg = dev->config;
734
735 uint8_t reg;
736
737 /* Switch to SENSOR register bank */
738 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_SENSOR);
739
740 /* Update COM8 to enable/disable automatic exposure control */
741 reg = ov2640_read_reg(&cfg->i2c, COM8);
742
743 if (enable) {
744 reg |= COM8_AEC_EN;
745 } else {
746 reg &= ~COM8_AEC_EN;
747 }
748
749 ret |= ov2640_write_reg(&cfg->i2c, COM8, reg);
750
751 return ret;
752 }
753
ov2640_set_horizontal_mirror(const struct device * dev,int enable)754 static int ov2640_set_horizontal_mirror(const struct device *dev,
755 int enable)
756 {
757 int ret = 0;
758 const struct ov2640_config *cfg = dev->config;
759
760 uint8_t reg;
761
762 /* Switch to SENSOR register bank */
763 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_SENSOR);
764
765 /* Update REG04 to enable/disable horizontal mirror */
766 reg = ov2640_read_reg(&cfg->i2c, REG04);
767
768 if (enable) {
769 reg |= REG04_HFLIP_IMG;
770 } else {
771 reg &= ~REG04_HFLIP_IMG;
772 }
773
774 ret |= ov2640_write_reg(&cfg->i2c, REG04, reg);
775
776 return ret;
777 }
778
ov2640_set_vertical_flip(const struct device * dev,int enable)779 static int ov2640_set_vertical_flip(const struct device *dev, int enable)
780 {
781 int ret = 0;
782 const struct ov2640_config *cfg = dev->config;
783
784 uint8_t reg;
785
786 /* Switch to SENSOR register bank */
787 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_SENSOR);
788
789 /* Update REG04 to enable/disable vertical flip */
790 reg = ov2640_read_reg(&cfg->i2c, REG04);
791
792 if (enable) {
793 reg |= REG04_VFLIP_IMG;
794 } else {
795 reg &= ~REG04_VFLIP_IMG;
796 }
797
798 ret |= ov2640_write_reg(&cfg->i2c, REG04, reg);
799
800 return ret;
801 }
802
ov2640_set_resolution(const struct device * dev,uint16_t img_width,uint16_t img_height)803 static int ov2640_set_resolution(const struct device *dev,
804 uint16_t img_width, uint16_t img_height)
805 {
806 int ret = 0;
807 const struct ov2640_config *cfg = dev->config;
808
809 uint16_t w = img_width;
810 uint16_t h = img_height;
811
812 /* Disable DSP */
813 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_DSP);
814 ret |= ov2640_write_reg(&cfg->i2c, R_BYPASS, R_BYPASS_DSP_BYPAS);
815
816 /* Write output width */
817 ret |= ov2640_write_reg(&cfg->i2c, ZMOW, (w >> 2) & 0xFF); /* OUTW[7:0] (real/4) */
818 ret |= ov2640_write_reg(&cfg->i2c, ZMOH, (h >> 2) & 0xFF); /* OUTH[7:0] (real/4) */
819 ret |= ov2640_write_reg(&cfg->i2c, ZMHH, ((h >> 8) & 0x04) |
820 ((w>>10) & 0x03)); /* OUTH[8]/OUTW[9:8] */
821
822 /* Set CLKRC */
823 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_SENSOR);
824 ret |= ov2640_write_reg(&cfg->i2c, CLKRC, 0x87);
825
826 /* Write DSP input registers */
827 ov2640_write_all(dev, uxga_regs, ARRAY_SIZE(uxga_regs));
828
829 /* Enable DSP */
830 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_DSP);
831 ret |= ov2640_write_reg(&cfg->i2c, R_BYPASS, R_BYPASS_DSP_EN);
832
833 k_msleep(30);
834
835 return ret;
836 }
837
ov2640_check_connection(const struct device * dev)838 uint8_t ov2640_check_connection(const struct device *dev)
839 {
840 int ret = 0;
841 const struct ov2640_config *cfg = dev->config;
842
843 uint8_t reg_pid_val, reg_ver_val;
844
845 ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_SENSOR);
846 reg_pid_val = ov2640_read_reg(&cfg->i2c, REG_PID);
847 reg_ver_val = ov2640_read_reg(&cfg->i2c, REG_VER);
848
849 if (REG_PID_VAL != reg_pid_val || REG_VER_VAL != reg_ver_val) {
850 LOG_ERR("OV2640 not detected\n");
851 return -ENODEV;
852 }
853
854 return ret;
855 }
856
ov2640_set_fmt(const struct device * dev,enum video_endpoint_id ep,struct video_format * fmt)857 static int ov2640_set_fmt(const struct device *dev,
858 enum video_endpoint_id ep, struct video_format *fmt)
859 {
860 struct ov2640_data *drv_data = dev->data;
861 uint16_t width, height;
862 int ret = 0;
863 int i = 0;
864
865 /* We only support RGB565 and JPEG pixel formats */
866 if (fmt->pixelformat != VIDEO_PIX_FMT_RGB565 && fmt->pixelformat != VIDEO_PIX_FMT_JPEG) {
867 LOG_ERR("ov2640 camera supports only RGB565 and JPG pixelformats!");
868 return -ENOTSUP;
869 }
870
871 width = fmt->width;
872 height = fmt->height;
873
874 if (!memcmp(&drv_data->fmt, fmt, sizeof(drv_data->fmt))) {
875 /* nothing to do */
876 return 0;
877 }
878
879 drv_data->fmt = *fmt;
880
881 /* Set output format */
882 ret |= ov2640_set_output_format(dev, fmt->pixelformat);
883
884 /* Check if camera is capable of handling given format */
885 while (fmts[i].pixelformat) {
886 if (fmts[i].width_min == width && fmts[i].height_min == height &&
887 fmts[i].pixelformat == fmt->pixelformat) {
888 /* Set window size */
889 ret |= ov2640_set_resolution(dev, fmt->width, fmt->height);
890 return ret;
891 }
892 i++;
893 }
894
895 /* Camera is not capable of handling given format */
896 LOG_ERR("Image format not supported\n");
897 return -ENOTSUP;
898 }
899
ov2640_get_fmt(const struct device * dev,enum video_endpoint_id ep,struct video_format * fmt)900 static int ov2640_get_fmt(const struct device *dev,
901 enum video_endpoint_id ep, struct video_format *fmt)
902 {
903 struct ov2640_data *drv_data = dev->data;
904
905 *fmt = drv_data->fmt;
906
907 return 0;
908 }
909
ov2640_stream_start(const struct device * dev)910 static int ov2640_stream_start(const struct device *dev)
911 {
912 return 0;
913 }
914
ov2640_stream_stop(const struct device * dev)915 static int ov2640_stream_stop(const struct device *dev)
916 {
917 return 0;
918 }
919
ov2640_get_caps(const struct device * dev,enum video_endpoint_id ep,struct video_caps * caps)920 static int ov2640_get_caps(const struct device *dev,
921 enum video_endpoint_id ep,
922 struct video_caps *caps)
923 {
924 caps->format_caps = fmts;
925 return 0;
926 }
927
ov2640_set_ctrl(const struct device * dev,unsigned int cid,void * value)928 static int ov2640_set_ctrl(const struct device *dev,
929 unsigned int cid, void *value)
930 {
931 int ret = 0;
932
933 switch (cid) {
934 case VIDEO_CID_HFLIP:
935 ret |= ov2640_set_horizontal_mirror(dev, (int)value);
936 break;
937 case VIDEO_CID_VFLIP:
938 ret |= ov2640_set_vertical_flip(dev, (int)value);
939 break;
940 case VIDEO_CID_CAMERA_EXPOSURE:
941 ret |= ov2640_set_exposure_ctrl(dev, (int)value);
942 break;
943 case VIDEO_CID_CAMERA_GAIN:
944 ret |= ov2640_set_gain_ctrl(dev, (int)value);
945 break;
946 case VIDEO_CID_CAMERA_BRIGHTNESS:
947 ret |= ov2640_set_brightness(dev, (int)value);
948 break;
949 case VIDEO_CID_CAMERA_SATURATION:
950 ret |= ov2640_set_saturation(dev, (int)value);
951 break;
952 case VIDEO_CID_CAMERA_WHITE_BAL:
953 ret |= ov2640_set_white_bal(dev, (int)value);
954 break;
955 case VIDEO_CID_CAMERA_CONTRAST:
956 ret |= ov2640_set_contrast(dev, (int)value);
957 break;
958 case VIDEO_CID_CAMERA_COLORBAR:
959 ret |= ov2640_set_colorbar(dev, (int)value);
960 break;
961 case VIDEO_CID_CAMERA_QUALITY:
962 ret |= ov2640_set_quality(dev, (int)value);
963 break;
964 default:
965 return -ENOTSUP;
966 }
967
968 return ret;
969 }
970
971 static const struct video_driver_api ov2640_driver_api = {
972 .set_format = ov2640_set_fmt,
973 .get_format = ov2640_get_fmt,
974 .get_caps = ov2640_get_caps,
975 .stream_start = ov2640_stream_start,
976 .stream_stop = ov2640_stream_stop,
977 .set_ctrl = ov2640_set_ctrl,
978 };
979
ov2640_init(const struct device * dev)980 static int ov2640_init(const struct device *dev)
981 {
982 struct video_format fmt;
983 int ret = 0;
984
985 #if DT_INST_NODE_HAS_PROP(0, reset_gpios)
986 const struct ov2640_config *cfg = dev->config;
987
988 ret = gpio_pin_configure_dt(&cfg->reset_gpio, GPIO_OUTPUT_ACTIVE);
989 if (ret) {
990 return ret;
991 }
992
993 gpio_pin_set_dt(&cfg->reset_gpio, 0);
994 k_sleep(K_MSEC(1));
995 gpio_pin_set_dt(&cfg->reset_gpio, 1);
996 k_sleep(K_MSEC(1));
997 #endif
998
999 ret = ov2640_check_connection(dev);
1000
1001 if (ret) {
1002 return ret;
1003 }
1004
1005 ov2640_soft_reset(dev);
1006 k_msleep(300);
1007
1008 ov2640_write_all(dev, default_regs, ARRAY_SIZE(default_regs));
1009
1010 /* set default/init format SVGA RGB565 */
1011 fmt.pixelformat = VIDEO_PIX_FMT_RGB565;
1012 fmt.width = SVGA_HSIZE;
1013 fmt.height = SVGA_VSIZE;
1014 fmt.pitch = SVGA_HSIZE * 2;
1015 ret = ov2640_set_fmt(dev, VIDEO_EP_OUT, &fmt);
1016 if (ret) {
1017 LOG_ERR("Unable to configure default format");
1018 return -EIO;
1019 }
1020
1021 ret |= ov2640_set_exposure_ctrl(dev, 1);
1022 ret |= ov2640_set_white_bal(dev, 1);
1023
1024 return ret;
1025 }
1026
1027 /* Unique Instance */
1028 static const struct ov2640_config ov2640_cfg_0 = {
1029 .i2c = I2C_DT_SPEC_INST_GET(0),
1030 #if DT_INST_NODE_HAS_PROP(0, reset_gpios)
1031 .reset_gpio = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
1032 #endif
1033 };
1034 static struct ov2640_data ov2640_data_0;
1035
ov2640_init_0(const struct device * dev)1036 static int ov2640_init_0(const struct device *dev)
1037 {
1038 const struct ov2640_config *cfg = dev->config;
1039
1040 if (!device_is_ready(cfg->i2c.bus)) {
1041 LOG_ERR("Bus device is not ready");
1042 return -ENODEV;
1043 }
1044
1045 #if DT_INST_NODE_HAS_PROP(0, reset_gpios)
1046 if (!gpio_is_ready_dt(&cfg->reset_gpio)) {
1047 LOG_ERR("%s: device %s is not ready", dev->name,
1048 cfg->reset_gpio.port->name);
1049 return -ENODEV;
1050 }
1051 #endif
1052
1053 uint32_t i2c_cfg = I2C_MODE_CONTROLLER |
1054 I2C_SPEED_SET(I2C_SPEED_STANDARD);
1055
1056 if (i2c_configure(cfg->i2c.bus, i2c_cfg)) {
1057 LOG_ERR("Failed to configure ov2640 i2c interface.");
1058 }
1059
1060 return ov2640_init(dev);
1061 }
1062
1063 DEVICE_DT_INST_DEFINE(0, &ov2640_init_0, NULL,
1064 &ov2640_data_0, &ov2640_cfg_0,
1065 POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY,
1066 &ov2640_driver_api);
1067
