1 /* ns16550.c - NS16550D serial driver */
2
3 #define DT_DRV_COMPAT ns16550
4
5 /*
6 * Copyright (c) 2010, 2012-2015 Wind River Systems, Inc.
7 * Copyright (c) 2020-2023 Intel Corp.
8 *
9 * SPDX-License-Identifier: Apache-2.0
10 */
11
12 /**
13 * @brief NS16550 Serial Driver
14 *
15 * This is the driver for the Intel NS16550 UART Chip used on the PC 386.
16 * It uses the SCCs in asynchronous mode only.
17 *
18 * Before individual UART port can be used, uart_ns16550_port_init() has to be
19 * called to setup the port.
20 */
21
22 #include <errno.h>
23 #include <zephyr/kernel.h>
24 #include <zephyr/arch/cpu.h>
25 #include <zephyr/types.h>
26
27 #include <zephyr/init.h>
28 #include <zephyr/toolchain.h>
29 #include <zephyr/linker/sections.h>
30 #include <zephyr/drivers/uart.h>
31 #include <zephyr/drivers/clock_control.h>
32 #include <zephyr/pm/policy.h>
33 #include <zephyr/sys/sys_io.h>
34 #include <zephyr/spinlock.h>
35 #include <zephyr/irq.h>
36
37 #if defined(CONFIG_PINCTRL)
38 #include <zephyr/drivers/pinctrl.h>
39 #endif
40
41 #include <zephyr/drivers/serial/uart_ns16550.h>
42 #include <zephyr/logging/log.h>
43
44 LOG_MODULE_REGISTER(uart_ns16550, CONFIG_UART_LOG_LEVEL);
45
46 #define UART_NS16550_PCP_ENABLED DT_ANY_INST_HAS_PROP_STATUS_OKAY(pcp)
47 #define UART_NS16550_DLF_ENABLED DT_ANY_INST_HAS_PROP_STATUS_OKAY(dlf)
48
49 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
50 BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
51 #include <zephyr/drivers/pcie/pcie.h>
52 #endif
53
54 /* Is UART module 'resets' line property defined */
55 #define UART_NS16550_RESET_ENABLED DT_ANY_INST_HAS_PROP_STATUS_OKAY(resets)
56
57 #if UART_NS16550_RESET_ENABLED
58 #include <zephyr/drivers/reset.h>
59 #endif
60
61 /* If any node has property io-mapped set, we need to support IO port
62 * access in the code and device config struct.
63 *
64 * Note that DT_ANY_INST_HAS_PROP_STATUS_OKAY() always returns true
65 * as io-mapped property is considered always exists and present,
66 * even if its value is zero. Therefore we cannot use it, and has to
67 * resort to the follow helper to see if any okay nodes have io-mapped
68 * as 1.
69 */
70 #define UART_NS16550_DT_PROP_IOMAPPED_HELPER(inst, prop, def) \
71 DT_INST_PROP_OR(inst, prop, def) ||
72
73 #define UART_NS16550_IOPORT_ENABLED \
74 (DT_INST_FOREACH_STATUS_OKAY_VARGS(UART_NS16550_DT_PROP_IOMAPPED_HELPER, io_mapped, 0) 0)
75
76 /* register definitions */
77
78 #define REG_THR 0x00 /* Transmitter holding reg. */
79 #define REG_RDR 0x00 /* Receiver data reg. */
80 #define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
81 #define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
82 #define REG_IER 0x01 /* Interrupt enable reg. */
83 #define REG_IIR 0x02 /* Interrupt ID reg. */
84 #define REG_FCR 0x02 /* FIFO control reg. */
85 #define REG_LCR 0x03 /* Line control reg. */
86 #define REG_MDC 0x04 /* Modem control reg. */
87 #define REG_LSR 0x05 /* Line status reg. */
88 #define REG_MSR 0x06 /* Modem status reg. */
89 #define REG_DLF 0xC0 /* Divisor Latch Fraction */
90 #define REG_PCP 0x200 /* PRV_CLOCK_PARAMS (Apollo Lake) */
91 #define REG_MDR1 0x08 /* Mode control reg. (TI_K3) */
92
93 /* equates for interrupt enable register */
94
95 #define IER_RXRDY 0x01 /* receiver data ready */
96 #define IER_TBE 0x02 /* transmit bit enable */
97 #define IER_LSR 0x04 /* line status interrupts */
98 #define IER_MSI 0x08 /* modem status interrupts */
99
100 /* equates for interrupt identification register */
101
102 #define IIR_MSTAT 0x00 /* modem status interrupt */
103 #define IIR_NIP 0x01 /* no interrupt pending */
104 #define IIR_THRE 0x02 /* transmit holding register empty interrupt */
105 #define IIR_RBRF 0x04 /* receiver buffer register full interrupt */
106 #define IIR_LS 0x06 /* receiver line status interrupt */
107 #define IIR_MASK 0x07 /* interrupt id bits mask */
108 #define IIR_ID 0x06 /* interrupt ID mask without NIP */
109 #define IIR_FE 0xC0 /* FIFO mode enabled */
110 #define IIR_CH 0x0C /* Character timeout*/
111
112 /* equates for FIFO control register */
113
114 #define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */
115 #define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */
116 #define FCR_XMITCLR 0x04 /* clear XMIT FIFO */
117
118 /* equates for Apollo Lake clock control register (PRV_CLOCK_PARAMS) */
119
120 #define PCP_UPDATE 0x80000000 /* update clock */
121 #define PCP_EN 0x00000001 /* enable clock output */
122
123 /* Fields for TI K3 UART module */
124
125 #define MDR1_MODE_SELECT_FIELD_MASK BIT_MASK(3)
126 #define MDR1_MODE_SELECT_FIELD_SHIFT BIT_MASK(0)
127
128 /* Modes available for TI K3 UART module */
129
130 #define MDR1_STD_MODE (0)
131 #define MDR1_SIR_MODE (1)
132 #define MDR1_UART_16X (2)
133 #define MDR1_UART_13X (3)
134 #define MDR1_MIR_MODE (4)
135 #define MDR1_FIR_MODE (5)
136 #define MDR1_CIR_MODE (6)
137 #define MDR1_DISABLE (7)
138
139 /*
140 * Per PC16550D (Literature Number: SNLS378B):
141 *
142 * RXRDY, Mode 0: When in the 16450 Mode (FCR0 = 0) or in
143 * the FIFO Mode (FCR0 = 1, FCR3 = 0) and there is at least 1
144 * character in the RCVR FIFO or RCVR holding register, the
145 * RXRDY pin (29) will be low active. Once it is activated the
146 * RXRDY pin will go inactive when there are no more charac-
147 * ters in the FIFO or holding register.
148 *
149 * RXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when the
150 * FCR3 = 1 and the trigger level or the timeout has been
151 * reached, the RXRDY pin will go low active. Once it is acti-
152 * vated it will go inactive when there are no more characters
153 * in the FIFO or holding register.
154 *
155 * TXRDY, Mode 0: In the 16450 Mode (FCR0 = 0) or in the
156 * FIFO Mode (FCR0 = 1, FCR3 = 0) and there are no charac-
157 * ters in the XMIT FIFO or XMIT holding register, the TXRDY
158 * pin (24) will be low active. Once it is activated the TXRDY
159 * pin will go inactive after the first character is loaded into the
160 * XMIT FIFO or holding register.
161 *
162 * TXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when
163 * FCR3 = 1 and there are no characters in the XMIT FIFO, the
164 * TXRDY pin will go low active. This pin will become inactive
165 * when the XMIT FIFO is completely full.
166 */
167 #define FCR_MODE0 0x00 /* set receiver in mode 0 */
168 #define FCR_MODE1 0x08 /* set receiver in mode 1 */
169
170 /* RCVR FIFO interrupt levels: trigger interrupt with this bytes in FIFO */
171 #define FCR_FIFO_1 0x00 /* 1 byte in RCVR FIFO */
172 #define FCR_FIFO_4 0x40 /* 4 bytes in RCVR FIFO */
173 #define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */
174 #define FCR_FIFO_14 0xC0 /* 14 bytes in RCVR FIFO */
175
176 /*
177 * UART NS16750 supports 64 bytes FIFO, which can be enabled
178 * via the FCR register
179 */
180 #define FCR_FIFO_64 0x20 /* Enable 64 bytes FIFO */
181
182 /* constants for line control register */
183
184 #define LCR_CS5 0x00 /* 5 bits data size */
185 #define LCR_CS6 0x01 /* 6 bits data size */
186 #define LCR_CS7 0x02 /* 7 bits data size */
187 #define LCR_CS8 0x03 /* 8 bits data size */
188 #define LCR_2_STB 0x04 /* 2 stop bits */
189 #define LCR_1_STB 0x00 /* 1 stop bit */
190 #define LCR_PEN 0x08 /* parity enable */
191 #define LCR_PDIS 0x00 /* parity disable */
192 #define LCR_EPS 0x10 /* even parity select */
193 #define LCR_SP 0x20 /* stick parity select */
194 #define LCR_SBRK 0x40 /* break control bit */
195 #define LCR_DLAB 0x80 /* divisor latch access enable */
196
197 /* constants for the modem control register */
198
199 #define MCR_DTR 0x01 /* dtr output */
200 #define MCR_RTS 0x02 /* rts output */
201 #define MCR_OUT1 0x04 /* output #1 */
202 #define MCR_OUT2 0x08 /* output #2 */
203 #define MCR_LOOP 0x10 /* loop back */
204 #define MCR_AFCE 0x20 /* auto flow control enable */
205
206 /* constants for line status register */
207
208 #define LSR_RXRDY 0x01 /* receiver data available */
209 #define LSR_OE 0x02 /* overrun error */
210 #define LSR_PE 0x04 /* parity error */
211 #define LSR_FE 0x08 /* framing error */
212 #define LSR_BI 0x10 /* break interrupt */
213 #define LSR_EOB_MASK 0x1E /* Error or Break mask */
214 #define LSR_THRE 0x20 /* transmit holding register empty */
215 #define LSR_TEMT 0x40 /* transmitter empty */
216
217 /* constants for modem status register */
218
219 #define MSR_DCTS 0x01 /* cts change */
220 #define MSR_DDSR 0x02 /* dsr change */
221 #define MSR_DRI 0x04 /* ring change */
222 #define MSR_DDCD 0x08 /* data carrier change */
223 #define MSR_CTS 0x10 /* complement of cts */
224 #define MSR_DSR 0x20 /* complement of dsr */
225 #define MSR_RI 0x40 /* complement of ring signal */
226 #define MSR_DCD 0x80 /* complement of dcd */
227
228 #define THR(dev) (get_port(dev) + REG_THR * reg_interval(dev))
229 #define RDR(dev) (get_port(dev) + REG_RDR * reg_interval(dev))
230 #define BRDL(dev) (get_port(dev) + REG_BRDL * reg_interval(dev))
231 #define BRDH(dev) (get_port(dev) + REG_BRDH * reg_interval(dev))
232 #define IER(dev) (get_port(dev) + REG_IER * reg_interval(dev))
233 #define IIR(dev) (get_port(dev) + REG_IIR * reg_interval(dev))
234 #define FCR(dev) (get_port(dev) + REG_FCR * reg_interval(dev))
235 #define LCR(dev) (get_port(dev) + REG_LCR * reg_interval(dev))
236 #define MDC(dev) (get_port(dev) + REG_MDC * reg_interval(dev))
237 #define LSR(dev) (get_port(dev) + REG_LSR * reg_interval(dev))
238 #define MSR(dev) (get_port(dev) + REG_MSR * reg_interval(dev))
239 #define MDR1(dev) (get_port(dev) + REG_MDR1 * reg_interval(dev))
240 #define DLF(dev) (get_port(dev) + REG_DLF)
241 #define PCP(dev) (get_port(dev) + REG_PCP)
242
243 #define IIRC(dev) (((struct uart_ns16550_dev_data *)(dev)->data)->iir_cache)
244
245 /* device config */
246 struct uart_ns16550_device_config {
247 union {
248 DEVICE_MMIO_ROM;
249 uint32_t port;
250 };
251 uint32_t sys_clk_freq;
252 const struct device *clock_dev;
253 clock_control_subsys_t clock_subsys;
254 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API)
255 uart_irq_config_func_t irq_config_func;
256 #endif
257 #if UART_NS16550_PCP_ENABLED
258 uint32_t pcp;
259 #endif
260 uint8_t reg_interval;
261 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
262 struct pcie_dev *pcie;
263 #endif
264 #if defined(CONFIG_PINCTRL)
265 const struct pinctrl_dev_config *pincfg;
266 #endif
267 #if UART_NS16550_IOPORT_ENABLED
268 bool io_map;
269 #endif
270 #if UART_NS16550_RESET_ENABLED
271 struct reset_dt_spec reset_spec;
272 #endif
273 };
274
275 /** Device data structure */
276 struct uart_ns16550_dev_data {
277 DEVICE_MMIO_RAM;
278 struct uart_config uart_config;
279 struct k_spinlock lock;
280 uint8_t fifo_size;
281
282 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
283 uint8_t iir_cache; /**< cache of IIR since it clears when read */
284 uart_irq_callback_user_data_t cb; /**< Callback function pointer */
285 void *cb_data; /**< Callback function arg */
286 #endif
287
288 #if UART_NS16550_DLF_ENABLED
289 uint8_t dlf; /**< DLF value */
290 #endif
291
292 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
293 bool tx_stream_on;
294 #endif
295 };
296
ns16550_outbyte(const struct uart_ns16550_device_config * cfg,uintptr_t port,uint8_t val)297 static void ns16550_outbyte(const struct uart_ns16550_device_config *cfg,
298 uintptr_t port, uint8_t val)
299 {
300 #if UART_NS16550_IOPORT_ENABLED
301 if (cfg->io_map) {
302 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
303 sys_out32(val, port);
304 } else {
305 sys_out8(val, port);
306 }
307 } else {
308 #else
309 {
310 #endif
311 /* MMIO mapped */
312 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
313 sys_write32(val, port);
314 } else {
315 sys_write8(val, port);
316 }
317 }
318 }
319
320 static uint8_t ns16550_inbyte(const struct uart_ns16550_device_config *cfg,
321 uintptr_t port)
322 {
323 #if UART_NS16550_IOPORT_ENABLED
324 if (cfg->io_map) {
325 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
326 return sys_in32(port);
327 } else {
328 return sys_in8(port);
329 }
330 } else {
331 #else
332 {
333 #endif
334 /* MMIO mapped */
335 if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
336 return sys_read32(port);
337 } else {
338 return sys_read8(port);
339 }
340 }
341 return 0;
342 }
343
344 #if UART_NS16550_PCP_ENABLED
345 static void ns16550_outword(const struct uart_ns16550_device_config *cfg,
346 uintptr_t port, uint32_t val)
347 {
348 #if UART_NS16550_IOPORT_ENABLED
349 if (cfg->io_map) {
350 sys_out32(val, port);
351 } else {
352 #else
353 {
354 #endif
355 /* MMIO mapped */
356 sys_write32(val, port);
357 }
358 }
359
360 static uint32_t ns16550_inword(const struct uart_ns16550_device_config *cfg,
361 uintptr_t port)
362 {
363 #if UART_NS16550_IOPORT_ENABLED
364 if (cfg->io_map) {
365 return sys_in32(port);
366 }
367 #endif
368 /* MMIO mapped */
369 return sys_read32(port);
370 }
371 #endif
372
373 static inline uint8_t reg_interval(const struct device *dev)
374 {
375 const struct uart_ns16550_device_config *config = dev->config;
376
377 return config->reg_interval;
378 }
379
380 static inline uintptr_t get_port(const struct device *dev)
381 {
382 uintptr_t port;
383 #if UART_NS16550_IOPORT_ENABLED
384 const struct uart_ns16550_device_config *config = dev->config;
385
386 if (config->io_map) {
387 port = config->port;
388 } else {
389 #else
390 {
391 #endif
392 port = DEVICE_MMIO_GET(dev);
393 }
394
395 return port;
396 }
397
398 static void set_baud_rate(const struct device *dev, uint32_t baud_rate, uint32_t pclk)
399 {
400 struct uart_ns16550_dev_data * const dev_data = dev->data;
401 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
402 uint32_t divisor; /* baud rate divisor */
403 uint8_t lcr_cache;
404
405 if ((baud_rate != 0U) && (pclk != 0U)) {
406 /*
407 * calculate baud rate divisor. a variant of
408 * (uint32_t)(pclk / (16.0 * baud_rate) + 0.5)
409 */
410 divisor = ((pclk + (baud_rate << 3))
411 / baud_rate) >> 4;
412
413 /* set the DLAB to access the baud rate divisor registers */
414 lcr_cache = ns16550_inbyte(dev_cfg, LCR(dev));
415 ns16550_outbyte(dev_cfg, LCR(dev), LCR_DLAB | lcr_cache);
416 ns16550_outbyte(dev_cfg, BRDL(dev), (unsigned char)(divisor & 0xff));
417 ns16550_outbyte(dev_cfg, BRDH(dev), (unsigned char)((divisor >> 8) & 0xff));
418
419 /* restore the DLAB to access the baud rate divisor registers */
420 ns16550_outbyte(dev_cfg, LCR(dev), lcr_cache);
421
422 dev_data->uart_config.baudrate = baud_rate;
423 }
424 }
425
426 static int uart_ns16550_configure(const struct device *dev,
427 const struct uart_config *cfg)
428 {
429 struct uart_ns16550_dev_data * const dev_data = dev->data;
430 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
431 uint8_t mdc = 0U;
432 uint32_t pclk = 0U;
433
434 /* temp for return value if error occurs in this locked region */
435 int ret = 0;
436
437 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
438
439 #if defined(CONFIG_PINCTRL)
440 if (dev_cfg->pincfg != NULL) {
441 pinctrl_apply_state(dev_cfg->pincfg, PINCTRL_STATE_DEFAULT);
442 }
443 #endif
444
445 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
446 dev_data->iir_cache = 0U;
447 #endif
448
449 #if UART_NS16550_DLF_ENABLED
450 ns16550_outbyte(dev_cfg, DLF(dev), dev_data->dlf);
451 #endif
452
453 #if UART_NS16550_PCP_ENABLED
454 uint32_t pcp = dev_cfg->pcp;
455
456 if (pcp) {
457 pcp |= PCP_EN;
458 ns16550_outbyte(dev_cfg, PCP(dev), pcp & ~PCP_UPDATE);
459 ns16550_outbyte(dev_cfg, PCP(dev), pcp | PCP_UPDATE);
460 }
461 #endif
462
463 #ifdef CONFIG_UART_NS16550_TI_K3
464 uint32_t mdr = ns16550_inbyte(dev_cfg, MDR1(dev));
465
466 mdr = ((mdr & ~MDR1_MODE_SELECT_FIELD_MASK) | ((((MDR1_STD_MODE) <<
467 MDR1_MODE_SELECT_FIELD_SHIFT)) & MDR1_MODE_SELECT_FIELD_MASK));
468 ns16550_outbyte(dev_cfg, MDR1(dev), mdr);
469 #endif
470 /*
471 * set clock frequency from clock_frequency property if valid,
472 * otherwise, get clock frequency from clock manager
473 */
474 if (dev_cfg->sys_clk_freq != 0U) {
475 pclk = dev_cfg->sys_clk_freq;
476 } else {
477 if (!device_is_ready(dev_cfg->clock_dev)) {
478 ret = -EINVAL;
479 goto out;
480 }
481
482 if (clock_control_get_rate(dev_cfg->clock_dev,
483 dev_cfg->clock_subsys,
484 &pclk) != 0) {
485 ret = -EINVAL;
486 goto out;
487 }
488 }
489
490 set_baud_rate(dev, cfg->baudrate, pclk);
491
492 /* Local structure to hold temporary values to pass to ns16550_outbyte() */
493 struct uart_config uart_cfg;
494
495 switch (cfg->data_bits) {
496 case UART_CFG_DATA_BITS_5:
497 uart_cfg.data_bits = LCR_CS5;
498 break;
499 case UART_CFG_DATA_BITS_6:
500 uart_cfg.data_bits = LCR_CS6;
501 break;
502 case UART_CFG_DATA_BITS_7:
503 uart_cfg.data_bits = LCR_CS7;
504 break;
505 case UART_CFG_DATA_BITS_8:
506 uart_cfg.data_bits = LCR_CS8;
507 break;
508 default:
509 ret = -ENOTSUP;
510 goto out;
511 }
512
513 switch (cfg->stop_bits) {
514 case UART_CFG_STOP_BITS_1:
515 uart_cfg.stop_bits = LCR_1_STB;
516 break;
517 case UART_CFG_STOP_BITS_2:
518 uart_cfg.stop_bits = LCR_2_STB;
519 break;
520 default:
521 ret = -ENOTSUP;
522 goto out;
523 }
524
525 switch (cfg->parity) {
526 case UART_CFG_PARITY_NONE:
527 uart_cfg.parity = LCR_PDIS;
528 break;
529 case UART_CFG_PARITY_EVEN:
530 uart_cfg.parity = LCR_EPS;
531 break;
532 default:
533 ret = -ENOTSUP;
534 goto out;
535 }
536
537 dev_data->uart_config = *cfg;
538
539 /* data bits, stop bits, parity, clear DLAB */
540 ns16550_outbyte(dev_cfg, LCR(dev),
541 uart_cfg.data_bits | uart_cfg.stop_bits | uart_cfg.parity);
542
543 mdc = MCR_OUT2 | MCR_RTS | MCR_DTR;
544 #if defined(CONFIG_UART_NS16550_VARIANT_NS16750) || \
545 defined(CONFIG_UART_NS16550_VARIANT_NS16950)
546 if (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS) {
547 mdc |= MCR_AFCE;
548 }
549 #endif
550
551 ns16550_outbyte(dev_cfg, MDC(dev), mdc);
552
553 /*
554 * Program FIFO: enabled, mode 0 (set for compatibility with quark),
555 * generate the interrupt at 8th byte
556 * Clear TX and RX FIFO
557 */
558 ns16550_outbyte(dev_cfg, FCR(dev),
559 FCR_FIFO | FCR_MODE0 | FCR_FIFO_8 | FCR_RCVRCLR | FCR_XMITCLR
560 #ifdef CONFIG_UART_NS16550_VARIANT_NS16750
561 | FCR_FIFO_64
562 #endif
563 );
564
565 if ((ns16550_inbyte(dev_cfg, IIR(dev)) & IIR_FE) == IIR_FE) {
566 #ifdef CONFIG_UART_NS16550_VARIANT_NS16750
567 dev_data->fifo_size = 64;
568 #elif defined(CONFIG_UART_NS16550_VARIANT_NS16950)
569 dev_data->fifo_size = 128;
570 #else
571 dev_data->fifo_size = 16;
572 #endif
573 } else {
574 dev_data->fifo_size = 1;
575 }
576
577 /* clear the port */
578 ns16550_inbyte(dev_cfg, RDR(dev));
579
580 /* disable interrupts */
581 ns16550_outbyte(dev_cfg, IER(dev), 0x00);
582
583 out:
584 k_spin_unlock(&dev_data->lock, key);
585 return ret;
586 };
587
588 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
589 static int uart_ns16550_config_get(const struct device *dev,
590 struct uart_config *cfg)
591 {
592 struct uart_ns16550_dev_data *data = dev->data;
593
594 cfg->baudrate = data->uart_config.baudrate;
595 cfg->parity = data->uart_config.parity;
596 cfg->stop_bits = data->uart_config.stop_bits;
597 cfg->data_bits = data->uart_config.data_bits;
598 cfg->flow_ctrl = data->uart_config.flow_ctrl;
599
600 return 0;
601 }
602 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
603
604 #if UART_NS16550_RESET_ENABLED
605 /**
606 * @brief Toggle the reset UART line
607 *
608 * This routine is called to bring UART IP out of reset state.
609 *
610 * @param reset_spec Reset controller device configuration struct
611 *
612 * @return 0 if successful, failed otherwise
613 */
614 static int uart_reset_config(const struct reset_dt_spec *reset_spec)
615 {
616 int ret;
617
618 if (!device_is_ready(reset_spec->dev)) {
619 LOG_ERR("Reset controller device is not ready");
620 return -ENODEV;
621 }
622
623 ret = reset_line_toggle(reset_spec->dev, reset_spec->id);
624 if (ret != 0) {
625 LOG_ERR("UART toggle reset line failed");
626 return ret;
627 }
628
629 return 0;
630 }
631 #endif /* UART_NS16550_RESET_ENABLED */
632
633 /**
634 * @brief Initialize individual UART port
635 *
636 * This routine is called to reset the chip in a quiescent state.
637 *
638 * @param dev UART device struct
639 *
640 * @return 0 if successful, failed otherwise
641 */
642 static int uart_ns16550_init(const struct device *dev)
643 {
644 struct uart_ns16550_dev_data *data = dev->data;
645 const struct uart_ns16550_device_config *dev_cfg = dev->config;
646 int ret;
647
648 ARG_UNUSED(dev_cfg);
649
650 #if UART_NS16550_RESET_ENABLED
651 /* Assert the UART reset line if it is defined. */
652 if (dev_cfg->reset_spec.dev != NULL) {
653 ret = uart_reset_config(&(dev_cfg->reset_spec));
654 if (ret != 0) {
655 return ret;
656 }
657 }
658 #endif
659
660 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie)
661 if (dev_cfg->pcie) {
662 struct pcie_bar mbar;
663
664 if (dev_cfg->pcie->bdf == PCIE_BDF_NONE) {
665 return -EINVAL;
666 }
667
668 pcie_probe_mbar(dev_cfg->pcie->bdf, 0, &mbar);
669 pcie_set_cmd(dev_cfg->pcie->bdf, PCIE_CONF_CMDSTAT_MEM, true);
670
671 device_map(DEVICE_MMIO_RAM_PTR(dev), mbar.phys_addr, mbar.size,
672 K_MEM_CACHE_NONE);
673 } else
674 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) */
675 {
676 #if UART_NS16550_IOPORT_ENABLED
677 /* Map directly from DTS */
678 if (!dev_cfg->io_map) {
679 #else
680 {
681 #endif
682 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
683 }
684 }
685
686 ret = uart_ns16550_configure(dev, &data->uart_config);
687 if (ret != 0) {
688 return ret;
689 }
690
691 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
692 dev_cfg->irq_config_func(dev);
693 #endif
694
695 return 0;
696 }
697
698 /**
699 * @brief Poll the device for input.
700 *
701 * @param dev UART device struct
702 * @param c Pointer to character
703 *
704 * @return 0 if a character arrived, -1 if the input buffer if empty.
705 */
706 static int uart_ns16550_poll_in(const struct device *dev, unsigned char *c)
707 {
708 struct uart_ns16550_dev_data *data = dev->data;
709 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
710 int ret = -1;
711 k_spinlock_key_t key = k_spin_lock(&data->lock);
712
713 if ((ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_RXRDY) != 0) {
714 /* got a character */
715 *c = ns16550_inbyte(dev_cfg, RDR(dev));
716 ret = 0;
717 }
718
719 k_spin_unlock(&data->lock, key);
720
721 return ret;
722 }
723
724 /**
725 * @brief Output a character in polled mode.
726 *
727 * Checks if the transmitter is empty. If empty, a character is written to
728 * the data register.
729 *
730 * If the hardware flow control is enabled then the handshake signal CTS has to
731 * be asserted in order to send a character.
732 *
733 * @param dev UART device struct
734 * @param c Character to send
735 */
736 static void uart_ns16550_poll_out(const struct device *dev,
737 unsigned char c)
738 {
739 struct uart_ns16550_dev_data *data = dev->data;
740 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
741 k_spinlock_key_t key = k_spin_lock(&data->lock);
742
743 while ((ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_THRE) == 0) {
744 }
745
746 ns16550_outbyte(dev_cfg, THR(dev), c);
747
748 k_spin_unlock(&data->lock, key);
749 }
750
751 /**
752 * @brief Check if an error was received
753 *
754 * @param dev UART device struct
755 *
756 * @return one of UART_ERROR_OVERRUN, UART_ERROR_PARITY, UART_ERROR_FRAMING,
757 * UART_BREAK if an error was detected, 0 otherwise.
758 */
759 static int uart_ns16550_err_check(const struct device *dev)
760 {
761 struct uart_ns16550_dev_data *data = dev->data;
762 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
763 k_spinlock_key_t key = k_spin_lock(&data->lock);
764 int check = (ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_EOB_MASK);
765
766 k_spin_unlock(&data->lock, key);
767
768 return check >> 1;
769 }
770
771 #if CONFIG_UART_INTERRUPT_DRIVEN
772
773 /**
774 * @brief Fill FIFO with data
775 *
776 * @param dev UART device struct
777 * @param tx_data Data to transmit
778 * @param size Number of bytes to send
779 *
780 * @return Number of bytes sent
781 */
782 static int uart_ns16550_fifo_fill(const struct device *dev,
783 const uint8_t *tx_data,
784 int size)
785 {
786 struct uart_ns16550_dev_data *data = dev->data;
787 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
788 int i;
789 k_spinlock_key_t key = k_spin_lock(&data->lock);
790
791 for (i = 0; (i < size) && (i < data->fifo_size); i++) {
792 ns16550_outbyte(dev_cfg, THR(dev), tx_data[i]);
793 }
794
795 k_spin_unlock(&data->lock, key);
796
797 return i;
798 }
799
800 /**
801 * @brief Read data from FIFO
802 *
803 * @param dev UART device struct
804 * @param rxData Data container
805 * @param size Container size
806 *
807 * @return Number of bytes read
808 */
809 static int uart_ns16550_fifo_read(const struct device *dev, uint8_t *rx_data,
810 const int size)
811 {
812 struct uart_ns16550_dev_data *data = dev->data;
813 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
814 int i;
815 k_spinlock_key_t key = k_spin_lock(&data->lock);
816
817 for (i = 0; (i < size) && (ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_RXRDY) != 0; i++) {
818 rx_data[i] = ns16550_inbyte(dev_cfg, RDR(dev));
819 }
820
821 k_spin_unlock(&data->lock, key);
822
823 return i;
824 }
825
826 /**
827 * @brief Enable TX interrupt in IER
828 *
829 * @param dev UART device struct
830 */
831 static void uart_ns16550_irq_tx_enable(const struct device *dev)
832 {
833 struct uart_ns16550_dev_data *data = dev->data;
834 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
835 k_spinlock_key_t key = k_spin_lock(&data->lock);
836
837 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
838 struct uart_ns16550_dev_data *const dev_data = dev->data;
839
840 if (!dev_data->tx_stream_on) {
841 dev_data->tx_stream_on = true;
842 uint8_t num_cpu_states;
843 const struct pm_state_info *cpu_states;
844
845 num_cpu_states = pm_state_cpu_get_all(0U, &cpu_states);
846
847 /*
848 * Power state to be disabled. Some platforms have multiple
849 * states and need to be given a constraint set according to
850 * different states.
851 */
852 for (uint8_t i = 0U; i < num_cpu_states; i++) {
853 pm_policy_state_lock_get(cpu_states[i].state, PM_ALL_SUBSTATES);
854 }
855 }
856 #endif
857 ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) | IER_TBE);
858
859 k_spin_unlock(&data->lock, key);
860 }
861
862 /**
863 * @brief Disable TX interrupt in IER
864 *
865 * @param dev UART device struct
866 */
867 static void uart_ns16550_irq_tx_disable(const struct device *dev)
868 {
869 struct uart_ns16550_dev_data *data = dev->data;
870 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
871 k_spinlock_key_t key = k_spin_lock(&data->lock);
872
873 ns16550_outbyte(dev_cfg, IER(dev),
874 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_TBE));
875
876 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
877 struct uart_ns16550_dev_data *const dev_data = dev->data;
878
879 if (dev_data->tx_stream_on) {
880 dev_data->tx_stream_on = false;
881 uint8_t num_cpu_states;
882 const struct pm_state_info *cpu_states;
883
884 num_cpu_states = pm_state_cpu_get_all(0U, &cpu_states);
885
886 /*
887 * Power state to be enabled. Some platforms have multiple
888 * states and need to be given a constraint release according
889 * to different states.
890 */
891 for (uint8_t i = 0U; i < num_cpu_states; i++) {
892 pm_policy_state_lock_put(cpu_states[i].state, PM_ALL_SUBSTATES);
893 }
894 }
895 #endif
896 k_spin_unlock(&data->lock, key);
897 }
898
899 /**
900 * @brief Check if Tx IRQ has been raised
901 *
902 * @param dev UART device struct
903 *
904 * @return 1 if an IRQ is ready, 0 otherwise
905 */
906 static int uart_ns16550_irq_tx_ready(const struct device *dev)
907 {
908 struct uart_ns16550_dev_data *data = dev->data;
909 k_spinlock_key_t key = k_spin_lock(&data->lock);
910
911 int ret = ((IIRC(dev) & IIR_ID) == IIR_THRE) ? 1 : 0;
912
913 k_spin_unlock(&data->lock, key);
914
915 return ret;
916 }
917
918 /**
919 * @brief Check if nothing remains to be transmitted
920 *
921 * @param dev UART device struct
922 *
923 * @return 1 if nothing remains to be transmitted, 0 otherwise
924 */
925 static int uart_ns16550_irq_tx_complete(const struct device *dev)
926 {
927 struct uart_ns16550_dev_data *data = dev->data;
928 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
929 k_spinlock_key_t key = k_spin_lock(&data->lock);
930
931 int ret = ((ns16550_inbyte(dev_cfg, LSR(dev)) & (LSR_TEMT | LSR_THRE))
932 == (LSR_TEMT | LSR_THRE)) ? 1 : 0;
933
934 k_spin_unlock(&data->lock, key);
935
936 return ret;
937 }
938
939 /**
940 * @brief Enable RX interrupt in IER
941 *
942 * @param dev UART device struct
943 */
944 static void uart_ns16550_irq_rx_enable(const struct device *dev)
945 {
946 struct uart_ns16550_dev_data *data = dev->data;
947 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
948 k_spinlock_key_t key = k_spin_lock(&data->lock);
949
950 ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) | IER_RXRDY);
951
952 k_spin_unlock(&data->lock, key);
953 }
954
955 /**
956 * @brief Disable RX interrupt in IER
957 *
958 * @param dev UART device struct
959 */
960 static void uart_ns16550_irq_rx_disable(const struct device *dev)
961 {
962 struct uart_ns16550_dev_data *data = dev->data;
963 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
964 k_spinlock_key_t key = k_spin_lock(&data->lock);
965
966 ns16550_outbyte(dev_cfg, IER(dev),
967 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_RXRDY));
968
969 k_spin_unlock(&data->lock, key);
970 }
971
972 /**
973 * @brief Check if Rx IRQ has been raised
974 *
975 * @param dev UART device struct
976 *
977 * @return 1 if an IRQ is ready, 0 otherwise
978 */
979 static int uart_ns16550_irq_rx_ready(const struct device *dev)
980 {
981 struct uart_ns16550_dev_data *data = dev->data;
982 k_spinlock_key_t key = k_spin_lock(&data->lock);
983
984 int ret = ((IIRC(dev) & IIR_ID) == IIR_RBRF) ? 1 : 0;
985
986 k_spin_unlock(&data->lock, key);
987
988 return ret;
989 }
990
991 /**
992 * @brief Enable error interrupt in IER
993 *
994 * @param dev UART device struct
995 */
996 static void uart_ns16550_irq_err_enable(const struct device *dev)
997 {
998 struct uart_ns16550_dev_data *data = dev->data;
999 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
1000 k_spinlock_key_t key = k_spin_lock(&data->lock);
1001
1002 ns16550_outbyte(dev_cfg, IER(dev),
1003 ns16550_inbyte(dev_cfg, IER(dev)) | IER_LSR);
1004
1005 k_spin_unlock(&data->lock, key);
1006 }
1007
1008 /**
1009 * @brief Disable error interrupt in IER
1010 *
1011 * @param dev UART device struct
1012 *
1013 * @return 1 if an IRQ is ready, 0 otherwise
1014 */
1015 static void uart_ns16550_irq_err_disable(const struct device *dev)
1016 {
1017 struct uart_ns16550_dev_data *data = dev->data;
1018 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
1019 k_spinlock_key_t key = k_spin_lock(&data->lock);
1020
1021 ns16550_outbyte(dev_cfg, IER(dev),
1022 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_LSR));
1023
1024 k_spin_unlock(&data->lock, key);
1025 }
1026
1027 /**
1028 * @brief Check if any IRQ is pending
1029 *
1030 * @param dev UART device struct
1031 *
1032 * @return 1 if an IRQ is pending, 0 otherwise
1033 */
1034 static int uart_ns16550_irq_is_pending(const struct device *dev)
1035 {
1036 struct uart_ns16550_dev_data *data = dev->data;
1037 k_spinlock_key_t key = k_spin_lock(&data->lock);
1038
1039 int ret = (!(IIRC(dev) & IIR_NIP)) ? 1 : 0;
1040
1041 k_spin_unlock(&data->lock, key);
1042
1043 return ret;
1044 }
1045
1046 /**
1047 * @brief Update cached contents of IIR
1048 *
1049 * @param dev UART device struct
1050 *
1051 * @return Always 1
1052 */
1053 static int uart_ns16550_irq_update(const struct device *dev)
1054 {
1055 struct uart_ns16550_dev_data *data = dev->data;
1056 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
1057 k_spinlock_key_t key = k_spin_lock(&data->lock);
1058
1059 IIRC(dev) = ns16550_inbyte(dev_cfg, IIR(dev));
1060
1061 k_spin_unlock(&data->lock, key);
1062
1063 return 1;
1064 }
1065
1066 /**
1067 * @brief Set the callback function pointer for IRQ.
1068 *
1069 * @param dev UART device struct
1070 * @param cb Callback function pointer.
1071 */
1072 static void uart_ns16550_irq_callback_set(const struct device *dev,
1073 uart_irq_callback_user_data_t cb,
1074 void *cb_data)
1075 {
1076 struct uart_ns16550_dev_data * const dev_data = dev->data;
1077 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
1078
1079 dev_data->cb = cb;
1080 dev_data->cb_data = cb_data;
1081
1082 k_spin_unlock(&dev_data->lock, key);
1083 }
1084
1085 /**
1086 * @brief Interrupt service routine.
1087 *
1088 * This simply calls the callback function, if one exists.
1089 *
1090 * @param arg Argument to ISR.
1091 */
1092 static void uart_ns16550_isr(const struct device *dev)
1093 {
1094 struct uart_ns16550_dev_data * const dev_data = dev->data;
1095
1096 if (dev_data->cb) {
1097 dev_data->cb(dev, dev_data->cb_data);
1098 }
1099
1100 #ifdef CONFIG_UART_NS16550_WA_ISR_REENABLE_INTERRUPT
1101 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
1102 uint8_t cached_ier = ns16550_inbyte(dev_cfg, IER(dev));
1103
1104 ns16550_outbyte(dev_cfg, IER(dev), 0U);
1105 ns16550_outbyte(dev_cfg, IER(dev), cached_ier);
1106 #endif
1107 }
1108
1109 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
1110
1111 #ifdef CONFIG_UART_NS16550_LINE_CTRL
1112
1113 /**
1114 * @brief Manipulate line control for UART.
1115 *
1116 * @param dev UART device struct
1117 * @param ctrl The line control to be manipulated
1118 * @param val Value to set the line control
1119 *
1120 * @return 0 if successful, failed otherwise
1121 */
1122 static int uart_ns16550_line_ctrl_set(const struct device *dev,
1123 uint32_t ctrl, uint32_t val)
1124 {
1125 struct uart_ns16550_dev_data *data = dev->data;
1126 const struct uart_ns16550_device_config *const dev_cfg = dev->config;
1127 uint32_t mdc, chg, pclk = 0U;
1128 k_spinlock_key_t key;
1129
1130 if (dev_cfg->sys_clk_freq != 0U) {
1131 pclk = dev_cfg->sys_clk_freq;
1132 } else {
1133 if (device_is_ready(dev_cfg->clock_dev)) {
1134 clock_control_get_rate(dev_cfg->clock_dev, dev_cfg->clock_subsys, &pclk);
1135 }
1136 }
1137
1138 switch (ctrl) {
1139 case UART_LINE_CTRL_BAUD_RATE:
1140 set_baud_rate(dev, val, pclk);
1141 return 0;
1142
1143 case UART_LINE_CTRL_RTS:
1144 case UART_LINE_CTRL_DTR:
1145 key = k_spin_lock(&data->lock);
1146 mdc = ns16550_inbyte(dev_cfg, MDC(dev));
1147
1148 if (ctrl == UART_LINE_CTRL_RTS) {
1149 chg = MCR_RTS;
1150 } else {
1151 chg = MCR_DTR;
1152 }
1153
1154 if (val) {
1155 mdc |= chg;
1156 } else {
1157 mdc &= ~(chg);
1158 }
1159 ns16550_outbyte(dev_cfg, MDC(dev), mdc);
1160 k_spin_unlock(&data->lock, key);
1161 return 0;
1162 }
1163
1164 return -ENOTSUP;
1165 }
1166
1167 #endif /* CONFIG_UART_NS16550_LINE_CTRL */
1168
1169 #ifdef CONFIG_UART_NS16550_DRV_CMD
1170
1171 /**
1172 * @brief Send extra command to driver
1173 *
1174 * @param dev UART device struct
1175 * @param cmd Command to driver
1176 * @param p Parameter to the command
1177 *
1178 * @return 0 if successful, failed otherwise
1179 */
1180 static int uart_ns16550_drv_cmd(const struct device *dev, uint32_t cmd,
1181 uint32_t p)
1182 {
1183 #if UART_NS16550_DLF_ENABLED
1184 if (cmd == CMD_SET_DLF) {
1185 struct uart_ns16550_dev_data * const dev_data = dev->data;
1186 const struct uart_ns16550_device_config * const dev_cfg = dev->config;
1187 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
1188
1189 dev_data->dlf = p;
1190 ns16550_outbyte(dev_cfg, DLF(dev), dev_data->dlf);
1191 k_spin_unlock(&dev_data->lock, key);
1192 return 0;
1193 }
1194 #endif
1195
1196 return -ENOTSUP;
1197 }
1198
1199 #endif /* CONFIG_UART_NS16550_DRV_CMD */
1200
1201
1202 static const struct uart_driver_api uart_ns16550_driver_api = {
1203 .poll_in = uart_ns16550_poll_in,
1204 .poll_out = uart_ns16550_poll_out,
1205 .err_check = uart_ns16550_err_check,
1206 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
1207 .configure = uart_ns16550_configure,
1208 .config_get = uart_ns16550_config_get,
1209 #endif
1210 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
1211
1212 .fifo_fill = uart_ns16550_fifo_fill,
1213 .fifo_read = uart_ns16550_fifo_read,
1214 .irq_tx_enable = uart_ns16550_irq_tx_enable,
1215 .irq_tx_disable = uart_ns16550_irq_tx_disable,
1216 .irq_tx_ready = uart_ns16550_irq_tx_ready,
1217 .irq_tx_complete = uart_ns16550_irq_tx_complete,
1218 .irq_rx_enable = uart_ns16550_irq_rx_enable,
1219 .irq_rx_disable = uart_ns16550_irq_rx_disable,
1220 .irq_rx_ready = uart_ns16550_irq_rx_ready,
1221 .irq_err_enable = uart_ns16550_irq_err_enable,
1222 .irq_err_disable = uart_ns16550_irq_err_disable,
1223 .irq_is_pending = uart_ns16550_irq_is_pending,
1224 .irq_update = uart_ns16550_irq_update,
1225 .irq_callback_set = uart_ns16550_irq_callback_set,
1226
1227 #endif
1228
1229 #ifdef CONFIG_UART_NS16550_LINE_CTRL
1230 .line_ctrl_set = uart_ns16550_line_ctrl_set,
1231 #endif
1232
1233 #ifdef CONFIG_UART_NS16550_DRV_CMD
1234 .drv_cmd = uart_ns16550_drv_cmd,
1235 #endif
1236 };
1237
1238 #define UART_NS16550_IRQ_FLAGS(n) \
1239 COND_CODE_1(DT_INST_IRQ_HAS_CELL(n, sense), \
1240 (DT_INST_IRQ(n, sense)), \
1241 (0))
1242
1243 /* IO-port or MMIO based UART */
1244 #define UART_NS16550_IRQ_CONFIG(n) \
1245 static void uart_ns16550_irq_config_func##n(const struct device *dev) \
1246 { \
1247 ARG_UNUSED(dev); \
1248 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
1249 uart_ns16550_isr, DEVICE_DT_INST_GET(n), \
1250 UART_NS16550_IRQ_FLAGS(n)); \
1251 irq_enable(DT_INST_IRQN(n)); \
1252 }
1253
1254 /* PCI(e) with auto IRQ detection */
1255 #define UART_NS16550_IRQ_CONFIG_PCIE(n) \
1256 static void uart_ns16550_irq_config_func##n(const struct device *dev) \
1257 { \
1258 BUILD_ASSERT(DT_INST_IRQN(n) == PCIE_IRQ_DETECT, \
1259 "Only runtime IRQ configuration is supported"); \
1260 BUILD_ASSERT(IS_ENABLED(CONFIG_DYNAMIC_INTERRUPTS), \
1261 "NS16550 PCIe requires dynamic interrupts"); \
1262 const struct uart_ns16550_device_config *dev_cfg = dev->config;\
1263 unsigned int irq = pcie_alloc_irq(dev_cfg->pcie->bdf); \
1264 if (irq == PCIE_CONF_INTR_IRQ_NONE) { \
1265 return; \
1266 } \
1267 pcie_connect_dynamic_irq(dev_cfg->pcie->bdf, irq, \
1268 DT_INST_IRQ(n, priority), \
1269 (void (*)(const void *))uart_ns16550_isr, \
1270 DEVICE_DT_INST_GET(n), \
1271 UART_NS16550_IRQ_FLAGS(n)); \
1272 pcie_irq_enable(dev_cfg->pcie->bdf, irq); \
1273 }
1274
1275 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
1276 #define DEV_CONFIG_IRQ_FUNC_INIT(n) \
1277 .irq_config_func = uart_ns16550_irq_config_func##n,
1278 #define UART_NS16550_IRQ_FUNC_DECLARE(n) \
1279 static void uart_ns16550_irq_config_func##n(const struct device *dev);
1280 #define UART_NS16550_IRQ_FUNC_DEFINE(n) \
1281 UART_NS16550_IRQ_CONFIG(n)
1282
1283 #define DEV_CONFIG_PCIE_IRQ_FUNC_INIT(n) \
1284 .irq_config_func = uart_ns16550_irq_config_func##n,
1285 #define UART_NS16550_PCIE_IRQ_FUNC_DECLARE(n) \
1286 static void uart_ns16550_irq_config_func##n(const struct device *dev);
1287 #define UART_NS16550_PCIE_IRQ_FUNC_DEFINE(n) \
1288 UART_NS16550_IRQ_CONFIG_PCIE(n)
1289 #else
1290 /* !CONFIG_UART_INTERRUPT_DRIVEN */
1291 #define DEV_CONFIG_IRQ_FUNC_INIT(n)
1292 #define UART_NS16550_IRQ_FUNC_DECLARE(n)
1293 #define UART_NS16550_IRQ_FUNC_DEFINE(n)
1294
1295 #define DEV_CONFIG_PCIE_IRQ_FUNC_INIT(n)
1296 #define UART_NS16550_PCIE_IRQ_FUNC_DECLARE(n)
1297 #define UART_NS16550_PCIE_IRQ_FUNC_DEFINE(n)
1298 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
1299
1300 #define UART_NS16550_COMMON_DEV_CFG_INITIALIZER(n) \
1301 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, clock_frequency), ( \
1302 .sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
1303 .clock_dev = NULL, \
1304 .clock_subsys = NULL, \
1305 ), ( \
1306 .sys_clk_freq = 0, \
1307 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
1308 .clock_subsys = (clock_control_subsys_t) DT_INST_PHA(\
1309 0, clocks, clkid), \
1310 ) \
1311 ) \
1312 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, pcp), \
1313 (.pcp = DT_INST_PROP_OR(n, pcp, 0),)) \
1314 .reg_interval = (1 << DT_INST_PROP(n, reg_shift)), \
1315 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, pinctrl_0), \
1316 (.pincfg = PINCTRL_DT_DEV_CONFIG_GET(DT_DRV_INST(n)),)) \
1317 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, resets), \
1318 (.reset_spec = RESET_DT_SPEC_INST_GET(n),))
1319
1320 #define UART_NS16550_COMMON_DEV_DATA_INITIALIZER(n) \
1321 .uart_config.baudrate = DT_INST_PROP_OR(n, current_speed, 0), \
1322 .uart_config.parity = UART_CFG_PARITY_NONE, \
1323 .uart_config.stop_bits = UART_CFG_STOP_BITS_1, \
1324 .uart_config.data_bits = UART_CFG_DATA_BITS_8, \
1325 .uart_config.flow_ctrl = \
1326 COND_CODE_1(DT_INST_PROP_OR(n, hw_flow_control, 0), \
1327 (UART_CFG_FLOW_CTRL_RTS_CTS), \
1328 (UART_CFG_FLOW_CTRL_NONE)), \
1329 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, dlf), \
1330 (.dlf = DT_INST_PROP_OR(n, dlf, 0),))
1331
1332 #define UART_NS16550_DEVICE_IO_MMIO_INIT(n) \
1333 UART_NS16550_IRQ_FUNC_DECLARE(n); \
1334 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, pinctrl_0), \
1335 (PINCTRL_DT_INST_DEFINE(n))); \
1336 static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_##n = { \
1337 COND_CODE_1(DT_INST_PROP_OR(n, io_mapped, 0), \
1338 (.port = DT_INST_REG_ADDR(n),), \
1339 (DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)),)) \
1340 IF_ENABLED(DT_INST_PROP_OR(n, io_mapped, 0), \
1341 (.io_map = true,)) \
1342 UART_NS16550_COMMON_DEV_CFG_INITIALIZER(n) \
1343 DEV_CONFIG_IRQ_FUNC_INIT(n) \
1344 }; \
1345 static struct uart_ns16550_dev_data uart_ns16550_dev_data_##n = { \
1346 UART_NS16550_COMMON_DEV_DATA_INITIALIZER(n) \
1347 }; \
1348 DEVICE_DT_INST_DEFINE(n, &uart_ns16550_init, NULL, \
1349 &uart_ns16550_dev_data_##n, &uart_ns16550_dev_cfg_##n, \
1350 PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
1351 &uart_ns16550_driver_api); \
1352 UART_NS16550_IRQ_FUNC_DEFINE(n)
1353
1354 #define UART_NS16550_DEVICE_PCIE_INIT(n) \
1355 UART_NS16550_PCIE_IRQ_FUNC_DECLARE(n); \
1356 DEVICE_PCIE_INST_DECLARE(n); \
1357 IF_ENABLED(DT_INST_NODE_HAS_PROP(n, pinctrl_0), \
1358 (PINCTRL_DT_INST_DEFINE(n))); \
1359 static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_##n = { \
1360 UART_NS16550_COMMON_DEV_CFG_INITIALIZER(n) \
1361 DEV_CONFIG_PCIE_IRQ_FUNC_INIT(n) \
1362 DEVICE_PCIE_INST_INIT(n, pcie) \
1363 }; \
1364 static struct uart_ns16550_dev_data uart_ns16550_dev_data_##n = { \
1365 UART_NS16550_COMMON_DEV_DATA_INITIALIZER(n) \
1366 }; \
1367 DEVICE_DT_INST_DEFINE(n, &uart_ns16550_init, NULL, \
1368 &uart_ns16550_dev_data_##n, &uart_ns16550_dev_cfg_##n, \
1369 COND_CODE_1(CONFIG_UART_NS16550_PARENT_INIT_LEVEL, \
1370 (POST_KERNEL), (PRE_KERNEL_1)), \
1371 CONFIG_SERIAL_INIT_PRIORITY, \
1372 &uart_ns16550_driver_api); \
1373 UART_NS16550_PCIE_IRQ_FUNC_DEFINE(n)
1374
1375 #define UART_NS16550_DEVICE_INIT(n) \
1376 COND_CODE_1(DT_INST_ON_BUS(n, pcie), \
1377 (UART_NS16550_DEVICE_PCIE_INIT(n)), \
1378 (UART_NS16550_DEVICE_IO_MMIO_INIT(n)))
1379
1380 DT_INST_FOREACH_STATUS_OKAY(UART_NS16550_DEVICE_INIT)
1381
