1 /*
2  * Copyright (c) 2022 Antmicro <www.antmicro.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #define DT_DRV_COMPAT sifive_pinctrl
8 
9 #include <zephyr/arch/cpu.h>
10 #include <zephyr/devicetree.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/dt-bindings/pinctrl/sifive-pinctrl.h>
13 
14 #include <soc.h>
15 
16 #define PINCTRL_BASE_ADDR	DT_INST_REG_ADDR(0)
17 #define PINCTRL_IOF_EN		(PINCTRL_BASE_ADDR + 0x0)
18 #define PINCTRL_IOF_SEL		(PINCTRL_BASE_ADDR + 0x4)
19 
pinctrl_sifive_set(uint32_t pin,uint32_t func)20 static int pinctrl_sifive_set(uint32_t pin, uint32_t func)
21 {
22 	uint32_t val;
23 
24 	if (func > SIFIVE_PINMUX_IOF1 || pin >= SIFIVE_PINMUX_PINS) {
25 		return -EINVAL;
26 	}
27 
28 	val = sys_read32(PINCTRL_IOF_SEL);
29 	if (func == SIFIVE_PINMUX_IOF1) {
30 		val |= (SIFIVE_PINMUX_IOF1 << pin);
31 	} else {
32 		val &= ~(SIFIVE_PINMUX_IOF1 << pin);
33 	}
34 	sys_write32(val, PINCTRL_IOF_SEL);
35 
36 	/* Enable IO function for this pin */
37 	val = sys_read32(PINCTRL_IOF_EN);
38 	val |= BIT(pin);
39 	sys_write32(val, PINCTRL_IOF_EN);
40 
41 	return 0;
42 }
43 
44 
pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)45 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
46 {
47 	ARG_UNUSED(reg);
48 	int i;
49 
50 	for (i = 0; i < pin_cnt; i++) {
51 		pinctrl_sifive_set(pins[i].pin, pins[i].iof);
52 	}
53 
54 	return 0;
55 }
56