1/*
2 * Copyright (c) 2018 Yurii Hamann
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/f7/stm32f746Xg.dtsi>
9#include <st/f7/stm32f746nghx-pinctrl.dtsi>
10#include "arduino_r3_connector.dtsi"
11#include <zephyr/dt-bindings/input/input-event-codes.h>
12#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
13#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14
15/ {
16	model = "STMicroelectronics STM32F746G DISCOVERY board";
17	compatible = "st,stm32f746g-disco";
18
19	chosen {
20		zephyr,console = &usart1;
21		zephyr,shell-uart = &usart1;
22		zephyr,sram = &sram0;
23		zephyr,flash = &flash0;
24		zephyr,dtcm = &dtcm;
25		zephyr,flash-controller = &n25q128a1;
26		zephyr,display = &ltdc;
27	};
28
29	leds {
30		compatible = "gpio-leds";
31		green_led_1: led_1 {
32			gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>;
33			label = "User LD1";
34		};
35	};
36
37	gpio_keys {
38		compatible = "gpio-keys";
39		user_button: button {
40			label = "User";
41			gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
42			zephyr,code = <INPUT_KEY_0>;
43		};
44	};
45
46	lvgl_pointer {
47		compatible = "zephyr,lvgl-pointer-input";
48		input = <&ft5336>;
49	};
50
51	sdram1: sdram@c0000000 {
52		compatible = "zephyr,memory-region", "mmio-sram";
53		device_type = "memory";
54		reg = <0xc0000000 DT_SIZE_M(16)>;
55		zephyr,memory-region = "SDRAM1";
56		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
57	};
58
59	aliases {
60		led0 = &green_led_1;
61		sw0 = &user_button;
62		spi-flash0 = &n25q128a1;
63	};
64};
65
66&clk_lsi {
67	status = "okay";
68};
69
70&clk_hse {
71	clock-frequency = <DT_FREQ_M(25)>;
72	status = "okay";
73};
74
75&pll {
76	div-m = <25>;
77	mul-n = <432>;
78	div-p = <2>;
79	div-q = <9>;
80	clocks = <&clk_hse>;
81	status = "okay";
82};
83
84&rcc {
85	clocks = <&pll>;
86	clock-frequency = <DT_FREQ_M(216)>;
87	ahb-prescaler = <1>;
88	apb1-prescaler = <4>;
89	apb2-prescaler = <2>;
90};
91
92&i2c1 {
93	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
94	pinctrl-names = "default";
95	status = "okay";
96	clock-frequency = <I2C_BITRATE_FAST>;
97};
98
99&i2c3 {
100	pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
101	pinctrl-names = "default";
102	status = "okay";
103	clock-frequency = <I2C_BITRATE_FAST>;
104
105	ft5336: ft5336@38 {
106		compatible = "focaltech,ft5336";
107		reg = <0x38>;
108		int-gpios = <&gpioi 13 0>;
109	};
110};
111
112&spi2 {
113	pinctrl-0 = <&spi2_sck_pi1 &spi2_miso_pb14 &spi2_mosi_pb15>;
114	pinctrl-names = "default";
115	cs-gpios = <&gpioa 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
116	status = "okay";
117};
118
119&usart1 {
120	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pb7>;
121	pinctrl-names = "default";
122	current-speed = <115200>;
123	status = "okay";
124};
125
126&usart6 {
127	pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
128	pinctrl-names = "default";
129	current-speed = <115200>;
130	status = "okay";
131};
132
133zephyr_udc0: &usbotg_fs {
134	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
135	pinctrl-names = "default";
136	status = "okay";
137};
138
139&timers3 {
140	st,prescaler = <10000>;
141	status = "okay";
142
143	pwm3: pwm {
144		status = "okay";
145		pinctrl-0 = <&tim3_ch1_pb4>;
146		pinctrl-names = "default";
147	};
148};
149
150&rtc {
151	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
152		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
153	status = "okay";
154
155	backup_regs {
156		status = "okay";
157	};
158};
159
160&sdmmc1 {
161	status = "okay";
162	pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
163		     &sdmmc1_d2_pc10 &sdmmc1_d3_pc11
164		     &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
165	pinctrl-names = "default";
166	cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
167};
168
169&mac {
170	status = "okay";
171	pinctrl-0 = <&eth_mdc_pc1
172		     &eth_rxd0_pc4
173		     &eth_rxd1_pc5
174		     &eth_ref_clk_pa1
175		     &eth_mdio_pa2
176		     &eth_crs_dv_pa7
177		     &eth_tx_en_pg11
178		     &eth_txd0_pg13
179		     &eth_txd1_pg14>;
180	pinctrl-names = "default";
181};
182
183&quadspi {
184	pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pb6
185		     &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pd12
186		     &quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pd13>;
187	pinctrl-names = "default";
188	status = "okay";
189
190	n25q128a1: qspi-nor-flash@0 {
191		compatible = "st,stm32-qspi-nor";
192		reg = <0>;
193		qspi-max-frequency = <72000000>;
194		size = <DT_SIZE_M(16*8)>;
195		status = "okay";
196
197		partitions {
198			compatible = "fixed-partitions";
199			#address-cells = <1>;
200			#size-cells = <1>;
201
202			slot1_partition: partition@0 {
203				label = "image-1";
204				reg = <0x00000000 DT_SIZE_K(640)>;
205				};
206
207			storage_partition: partition@a0000 {
208				label = "storage";
209				reg = <0x000a0000 DT_SIZE_M(15)>;
210			};
211		};
212	};
213};
214
215&fmc {
216	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
217		     &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke0_pc3
218		     &fmc_sdne0_ph3 &fmc_sdnras_pf11 &fmc_sdncas_pg15
219		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
220		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
221		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
222		     &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
223		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
224		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
225		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
226		     &fmc_d15_pd10>;
227	pinctrl-names = "default";
228	status = "okay";
229
230	sdram {
231		status = "okay";
232		power-up-delay = <100>;
233		num-auto-refresh = <8>;
234		mode-register = <0x220>;
235		/*
236		 * Auto refresh command shall be issued every 15.625 us
237		 * and is calculated as ((15.625 * SDRAM_CLK_MHZ) - 20)
238		 * Note: SDRAM_CLK_MHZ = HCLK_MHZ / 2 (108 MHz)
239		 */
240		refresh-rate = <1667>;
241		bank@0 {
242			reg = <0>;
243			st,sdram-control = <STM32_FMC_SDRAM_NC_8
244						STM32_FMC_SDRAM_NR_12
245						STM32_FMC_SDRAM_MWID_16
246						STM32_FMC_SDRAM_NB_4
247						STM32_FMC_SDRAM_CAS_2
248						STM32_FMC_SDRAM_SDCLK_PERIOD_2
249						STM32_FMC_SDRAM_RBURST_ENABLE
250						STM32_FMC_SDRAM_RPIPE_0>;
251			st,sdram-timing = <2 6 4 6 2 2 2>;
252		};
253	};
254};
255
256&ltdc {
257	pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
258		     &ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
259		     &ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
260		     &ltdc_g4_pj11 &ltdc_g5_pk0 &ltdc_g6_pk1 &ltdc_g7_pk2
261		     &ltdc_b0_pe4 &ltdc_b1_pj13 &ltdc_b2_pj14 &ltdc_b3_pj15
262		     &ltdc_b4_pg12 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
263		     &ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi10 &ltdc_vsync_pi9>;
264	pinctrl-names = "default";
265	disp-on-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
266	bl-ctrl-gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
267	ext-sdram = <&sdram1>;
268	status = "okay";
269
270	width = <480>;
271	height = <272>;
272	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
273	display-timings {
274		compatible = "zephyr,panel-timing";
275		de-active = <0>;
276		pixelclk-active = <0>;
277		hsync-active = <0>;
278		vsync-active = <0>;
279		hsync-len = <1>;
280		vsync-len = <10>;
281		hback-porch = <43>;
282		vback-porch = <12>;
283		hfront-porch = <8>;
284		vfront-porch = <4>;
285	};
286	def-back-color-red = <0xFF>;
287	def-back-color-green = <0xFF>;
288	def-back-color-blue = <0xFF>;
289};
290