1/*
2 * Copyright (c) 2018 Nathan Tsoi <nathan@vertile.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/f0/stm32f051X8.dtsi>
9#include <st/f0/stm32f051r8tx-pinctrl.dtsi>
10#include <zephyr/dt-bindings/input/input-event-codes.h>
11
12/ {
13	model = "STMicroelectronics STM32F0DISCOVERY board";
14	compatible = "st,stm32f058r8-discovery";
15
16	chosen {
17		zephyr,console = &usart1;
18		zephyr,shell-uart = &usart1;
19		zephyr,sram = &sram0;
20		zephyr,flash = &flash0;
21		zephyr,code-partition = &slot0_partition;
22	};
23
24	leds {
25		compatible = "gpio-leds";
26		green_led_3: led_3 {
27			gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>;
28			label = "User LD3";
29		};
30		blue_led_4: led_4 {
31			gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>;
32			label = "User LD4";
33		};
34	};
35
36	gpio_keys {
37		compatible = "gpio-keys";
38		user_button: button {
39			label = "Key";
40			gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
41			zephyr,code = <INPUT_KEY_0>;
42		};
43	};
44
45	aliases {
46		led0 = &green_led_3;
47		led1 = &blue_led_4;
48		sw0 = &user_button;
49		watchdog0 = &iwdg;
50	};
51};
52
53&clk_lsi {
54	status = "okay";
55};
56
57&clk_hse {
58	clock-frequency = <DT_FREQ_M(8)>;
59	status = "okay";
60};
61
62&pll {
63	prediv = <1>;
64	mul = <6>;
65	clocks = <&clk_hse>;
66	status = "okay";
67};
68
69&rcc {
70	clocks = <&pll>;
71	clock-frequency = <DT_FREQ_M(48)>;
72	ahb-prescaler = <1>;
73	apb1-prescaler = <1>;
74};
75
76/* Due to limited available memory, don't enable gpiod and gpiof */
77&gpiod {status = "disabled";};
78&gpiof {status = "disabled";};
79
80&usart1 {
81	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
82	pinctrl-names = "default";
83	current-speed = <115200>;
84	status = "okay";
85};
86
87&usart2 {
88	pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
89	pinctrl-names = "default";
90	current-speed = <115200>;
91	status = "okay";
92};
93
94&flash0 {
95	partitions {
96		compatible = "fixed-partitions";
97		#address-cells = <1>;
98		#size-cells = <1>;
99
100		boot_partition: partition@0 {
101			label = "mcuboot";
102			reg = <0x00000000 DT_SIZE_K(8)>;
103			read-only;
104		};
105
106		/*
107		 * The flash starting at offset 0x2000 and ending at
108		 * offset 0x3999 is reserved for use by the application.
109		 */
110
111		slot0_partition: partition@4000 {
112			label = "image-0";
113			reg = <0x00004000 DT_SIZE_K(16)>;
114		};
115		slot1_partition: partition@8000 {
116			label = "image-1";
117			reg = <0x00008000 DT_SIZE_K(16)>;
118		};
119		scratch_partition: partition@c000 {
120			label = "image-scratch";
121			reg = <0x0000C000 DT_SIZE_K(16)>;
122		};
123	};
124};
125
126&iwdg {
127	status = "okay";
128};
129
130&rtc {
131	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
132		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
133	status = "okay";
134
135	backup_regs {
136		status = "okay";
137	};
138};
139