1/*
2 * Copyright (c) 2018-2021 Linaro Limited
3 * Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/dts-v1/;
9
10#include <arm/armv8.1-m.dtsi>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13#include <mem.h>
14
15/ {
16	compatible = "arm,mps3-an547";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		led0 = &led_0;
22		led1 = &led_1;
23		sw0 = &user_button_0;
24		sw1 = &user_button_1;
25	};
26
27	chosen {
28		zephyr,console = &uart0;
29		zephyr,shell-uart = &uart0;
30		zephyr,sram = &dtcm;
31		zephyr,flash = &itcm;
32	};
33
34	leds {
35		compatible = "gpio-leds";
36		led_0: led_0 {
37			gpios = <&gpio_led0 0>;
38			label = "USERLED0";
39		};
40		led_1: led_1 {
41			gpios = <&gpio_led0 1>;
42			label = "USERLED1";
43		};
44		led_2: led_2 {
45			gpios = <&gpio_led0 2>;
46			label = "USERLED2";
47		};
48		led_3: led_3 {
49			gpios = <&gpio_led0 3>;
50			label = "USERLED3";
51		};
52		led_4: led_4 {
53			gpios = <&gpio_led0 4>;
54			label = "USERLED4";
55		};
56		led_5: led_5 {
57			gpios = <&gpio_led0 5>;
58			label = "USERLED5";
59		};
60		led_6: led_6 {
61			gpios = <&gpio_led0 6>;
62			label = "USERLED6";
63		};
64		led_7: led_7 {
65			gpios = <&gpio_led0 7>;
66			label = "USERLED7";
67		};
68		led_8: led_8 {
69			gpios = <&gpio_led0 8>;
70			label = "PB1LED";
71		};
72		led_9: led_9 {
73			gpios = <&gpio_led0 9>;
74			label = "PB2LED";
75		};
76	};
77
78	gpio_keys {
79		compatible = "gpio-keys";
80		user_button_0: button_0 {
81			label = "USERPB0";
82			gpios = <&gpio_button 0>;
83			zephyr,code = <INPUT_KEY_0>;
84		};
85		user_button_1: button_1 {
86			label = "USERPB1";
87			gpios = <&gpio_button 1>;
88			zephyr,code = <INPUT_KEY_1>;
89		};
90	};
91
92	ethosu {
93		#address-cells = <1>;
94		#size-cells = <0>;
95		interrupt-parent = <&nvic>;
96
97		ethosu0: ethosu@48102000 {
98			compatible = "arm,ethos-u";
99			reg = <0x48102000>;
100			interrupts = <56 3>;
101			secure-enable;
102			privilege-enable;
103			status = "okay";
104		};
105	};
106
107	cpus {
108		#address-cells = <1>;
109		#size-cells = <0>;
110
111		cpu@0 {
112			device_type = "cpu";
113			compatible = "arm,cortex-m55";
114			reg = <0>;
115			#address-cells = <1>;
116			#size-cells = <1>;
117
118			mpu: mpu@e000ed90 {
119				compatible = "arm,armv8.1m-mpu";
120				reg = <0xe000ed90 0x40>;
121				arm,num-mpu-regions = <16>;
122			};
123		};
124	};
125
126	/* We utilize the secure addresses, if you subtract 0x10000000
127	 * you'll get the non-secure alias
128	 */
129	itcm: itcm@10000000 {	/* alias @ 0x0 */
130		compatible = "zephyr,memory-region";
131		reg = <0x10000000 DT_SIZE_K(512)>;
132		zephyr,memory-region = "ITCM";
133	};
134
135	sram: sram@11000000 {	/* alias @ 0x01000000 */
136		compatible = "mmio-sram";
137		reg = <0x11000000 DT_SIZE_M(2)>;
138	};
139
140	dtcm: dtcm@30000000 {	/* alias @ 0x20000000 */
141		compatible = "zephyr,memory-region";
142		reg = <0x30000000 DT_SIZE_K(512)>;
143		zephyr,memory-region = "DTCM";
144	};
145
146	isram: sram@31000000 {/* alias @ 0x21000000 */
147		compatible = "mmio-sram";
148		reg = <0x31000000 DT_SIZE_M(4)>;
149	};
150
151	/* DDR4 - 2G, alternates non-secure/secure every 256M */
152	ddr4: memory@60000000 {
153		device_type = "memory";
154		compatible = "zephyr,memory-region";
155		reg = <0x60000000 DT_SIZE_M(256)
156		       0x70000000 DT_SIZE_M(256)
157		       0x80000000 DT_SIZE_M(256)
158		       0x90000000 DT_SIZE_M(256)
159		       0xa0000000 DT_SIZE_M(256)
160		       0xb0000000 DT_SIZE_M(256)
161		       0xc0000000 DT_SIZE_M(256)
162		       0xd0000000 DT_SIZE_M(256)>;
163		zephyr,memory-region = "DDR4";
164	};
165
166	soc {
167		peripheral@50000000 {
168			#address-cells = <1>;
169			#size-cells = <1>;
170			ranges = <0x0 0x50000000 0x10000000>;
171
172			#include "mps3_an547-common.dtsi"
173		};
174	};
175};
176
177&nvic {
178	arm,num-irq-priority-bits = <3>;
179};
180