1/*
2 * Copyright (c) 2018-2019 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <mem.h>
10#include <arm/armv8-m.dtsi>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13
14/ {
15	compatible = "arm,mps2";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		led0 = &led_0;
21		led1 = &led_1;
22		sw0 = &user_button_0;
23		sw1 = &user_button_1;
24		watchdog0 = &wdog0;
25	};
26
27	chosen {
28		zephyr,console = &uart0;
29		zephyr,shell-uart = &uart0;
30		zephyr,sram = &ram;
31		zephyr,flash = &code;
32	};
33
34	leds {
35		compatible = "gpio-leds";
36		led_0: led_0 {
37			gpios = <&gpio_led0 0>;
38			label = "USERLED0";
39		};
40		led_1: led_1 {
41			gpios = <&gpio_led0 1>;
42			label = "USERLED1";
43		};
44	};
45
46	gpio_keys {
47		compatible = "gpio-keys";
48		user_button_0: button_0 {
49			label = "USERPB0";
50			gpios = <&gpio_button 0>;
51			zephyr,code = <INPUT_KEY_0>;
52		};
53		user_button_1: button_1 {
54			label = "USERPB1";
55			gpios = <&gpio_button 1>;
56			zephyr,code = <INPUT_KEY_1>;
57		};
58	};
59
60	cpus {
61		#address-cells = <1>;
62		#size-cells = <0>;
63
64		cpu@0 {
65			device_type = "cpu";
66			compatible = "arm,cortex-m33";
67			reg = <0>;
68			#address-cells = <1>;
69			#size-cells = <1>;
70
71			mpu: mpu@e000ed90 {
72				compatible = "arm,armv8m-mpu";
73				reg = <0xe000ed90 0x40>;
74				arm,num-mpu-regions = <16>;
75			};
76		};
77	};
78
79	/*
80	 * The memory regions defined below are according to AN521:
81	 * https://documentation-service.arm.com/static/5fa12fe9b1a7c5445f29017f
82	 *
83	 * Please see tables mentioned in individual comments below for details.
84	 */
85
86	ssram1: memory@0 {
87		/* Table 3-2, row 1. */
88		compatible = "zephyr,memory-region", "mmio-sram";
89		reg = <0x0 DT_SIZE_M(4)>;
90		zephyr,memory-region = "SSRAM1";
91	};
92
93	ssram2_3: memory@28000000 {
94		/* Table 3-4, rows 8 and 9. */
95		compatible = "zephyr,memory-region", "mmio-sram";
96		reg = <0x28000000 DT_SIZE_M(4)>;
97		zephyr,memory-region = "SSRAM2_3";
98	};
99
100	psram: memory@80000000 {
101		/* Table 3-6, row 1. */
102		device_type = "memory";
103		reg = <0x80000000 DT_SIZE_M(16)>;
104	};
105
106	reserved-memory {
107		#address-cells = <1>;
108		#size-cells = <1>;
109		ranges;
110
111		/* This code memory region must match what the TF-M
112		 * project has defined for that board - a single image boot is
113		 * assumed. Please see the memory layout in:
114		 *
115		 * https://github.com/zephyrproject-rtos/trusted-firmware-m/blob/master/platform/ext/target/arm/mps2/an521/partition/flash_layout.h
116		 */
117		code: memory@100000 {
118			reg = <0x00100000 DT_SIZE_K(512)>;
119		};
120
121		/* This ram memory region's size is chosen to avoid conflict
122		 * with the mps2_an521_remote board's RAM region.
123		 *
124		 * Its available address space must be compatible with what
125		 * TF-M assigns to NS firmware.
126		 */
127		ram: memory@28100000 {
128			reg = <0x28100000 DT_SIZE_K(512)>;
129		};
130	};
131
132	soc {
133		peripheral@40000000 {
134			#address-cells = <1>;
135			#size-cells = <1>;
136			ranges = <0x0 0x40000000 0x10000000>;
137
138			#include "mps2_an521-common.dtsi"
139		};
140	};
141};
142
143&nvic {
144	arm,num-irq-priority-bits = <3>;
145};
146