1 /*
2  * Copyright (c) 2020,  NXP
3  * SPDX-License-Identifier: Apache-2.0
4  */
5 
6 #include <zephyr/init.h>
7 #include <zephyr/devicetree.h>
8 #include <fsl_device_registers.h>
9 
mimxrt685_evk_init(void)10 static int mimxrt685_evk_init(void)
11 {
12 
13 /* flexcomm1 and flexcomm3 are configured to loopback the TX signal to RX */
14 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay)) && \
15 	(DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay)) && \
16 	CONFIG_I2S
17 
18 	/* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm3 */
19 	SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(3) |
20 				SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(3);
21 
22 #ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
23 	/* Select Data in from Transmit I2S - Flexcomm 3 */
24 	SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(3);
25 	/* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */
26 	SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(1);
27 #endif
28 
29 	/* Set Receive I2S - Flexcomm 1 SCK, WS from shared signal set 0 */
30 	SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
31 				SYSCTL1_FCCTRLSEL_WSINSEL(1);
32 
33 	/* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */
34 	SYSCTL1->FCCTRLSEL[3] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
35 				SYSCTL1_FCCTRLSEL_WSINSEL(1);
36 
37 #ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
38 	/* Select Receive I2S - Flexcomm 1 Data in from shared signal set 0 */
39 	SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1);
40 	/* Select Transmit I2S - Flexcomm 3 Data out to shared signal set 0 */
41 	SYSCTL1->FCCTRLSEL[3] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1);
42 #endif
43 
44 #endif
45 
46 #ifdef CONFIG_REBOOT
47 	/*
48 	 * The sys_reboot API calls NVIC_SystemReset. On the RT685, the warm
49 	 * reset will not complete correctly unless the ROM toggles the
50 	 * flash reset pin. We can control this behavior using the OTP shadow
51 	 * register for OPT word BOOT_CFG1
52 	 *
53 	 * Set FLEXSPI_RESET_PIN_ENABLE=1, FLEXSPI_RESET_PIN= PIO2_12
54 	 */
55 	 OCOTP->OTP_SHADOW[97] = 0x314000;
56 #endif /* CONFIG_REBOOT */
57 
58 	return 0;
59 }
60 
61 SYS_INIT(mimxrt685_evk_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
62