1/*
2 * Copyright (c) 2019, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <nxp/nxp_lpc55S6x.dtsi>
10#include "lpcxpresso55s69.dtsi"
11#include <zephyr/dt-bindings/pwm/pwm.h>
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13
14/ {
15	model = "NXP LPCXpresso55S69 board";
16	compatible = "nxp,lpc55xxx", "nxp,lpc";
17
18	cpus {
19		/delete-node/ cpu@1;
20	};
21
22	aliases{
23		sw0 = &user_button_1;
24		sw1 = &user_button_2;
25		sw2 = &user_button_3;
26		watchdog0 = &wwdt0;
27		/* For pwm test suites */
28		pwm-0 = &sc_timer;
29		pwm-led0 = &red_pwm_led;
30		red-pwm-led = &red_pwm_led;
31		sdhc0 = &sdhc0;
32		accel0 = &mma8652fc;
33		sdhc0 = &sdif;
34	};
35
36	chosen {
37		zephyr,sram = &sram0;
38		zephyr,flash = &flash0;
39		zephyr,code-partition = &slot0_partition;
40		zephyr,code-cpu1-partition = &slot1_partition;
41		zephyr,sram-cpu1-partition = &sram3;
42		zephyr,console = &flexcomm0;
43		zephyr,shell-uart = &flexcomm0;
44		zephyr,entropy = &rng;
45	};
46
47	gpio_keys {
48		compatible = "gpio-keys";
49		user_button_1: button_0 {
50			label = "User SW1";
51			gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
52			zephyr,code = <INPUT_KEY_0>;
53		};
54		user_button_2: button_1 {
55			label = "User SW2";
56			gpios = <&gpio1 18 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
57			zephyr,code = <INPUT_KEY_1>;
58		};
59		user_button_3: button_2 {
60			label = "User SW3";
61			gpios = <&gpio1 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
62			zephyr,code = <INPUT_KEY_2>;
63		};
64	};
65
66	pwmleds {
67		compatible = "pwm-leds";
68		red_pwm_led: red_pwm_led {
69			pwms = <&sc_timer 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
70			label = "Red PWM LED";
71			status = "okay";
72		};
73	};
74};
75
76/*
77 * Default for this board is to allocate SRAM0-2 to cpu0 but the
78 * application can have an application specific device tree to
79 * allocate the SRAM0-4 differently.
80 *
81 * For example, SRAM0-3 could be allocated to cpu0 with only SRAM4
82 * for cpu1. This would require the zephyr,sram chosen value for cpu1
83 * to be changed to sram4 and the value of sram0 to have a DT_SIZE_K
84 * of 256.
85 *
86 */
87&sram0 {
88	compatible = "mmio-sram";
89	reg = <0x20000000 DT_SIZE_K(192)>;
90};
91
92&gpio0 {
93	status = "okay";
94};
95
96&gpio1 {
97	status = "okay";
98};
99
100&green_led {
101	status = "okay";
102};
103
104&red_led {
105	status = "okay";
106};
107
108&flexcomm0 {
109	status = "okay";
110};
111
112&flexcomm4 {
113	status = "okay";
114};
115
116&sdif {
117	status = "okay";
118	pinctrl-0 = <&pinmux_sdif_default>;
119	pinctrl-names = "default";
120	mmc {
121		compatible = "zephyr,sdmmc-disk";
122		status = "okay";
123	};
124};
125
126&hs_lspi {
127	status = "okay";
128	dmas = <&dma0 2>, <&dma0 3>;
129	dma-names = "rx", "tx";
130	cs-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
131};
132
133&wwdt0 {
134	status = "okay";
135};
136
137&adc0 {
138	status = "okay";
139	pinctrl-0 = <&pinmux_lpadc0>;
140	pinctrl-names = "default";
141};
142
143&mailbox0 {
144	status = "okay";
145};
146
147&usbfs {
148	pinctrl-0 = <&pinmux_usbfs>;
149	pinctrl-names = "default";
150};
151
152zephyr_udc0: &usbhs {
153	status = "okay";
154};
155
156&ctimer0 {
157	status = "okay";
158};
159
160&ctimer1 {
161	status = "okay";
162};
163
164&ctimer2 {
165	status = "okay";
166};
167
168&ctimer3 {
169	status = "okay";
170};
171
172&ctimer4 {
173	status = "okay";
174};
175
176/* I2S receive channel */
177i2s0: &flexcomm6 {
178	status = "okay";
179	compatible = "nxp,lpc-i2s";
180	#address-cells = <1>;
181	#size-cells = <0>;
182	dmas = <&dma0 16>;
183	dma-names = "rx";
184};
185
186/* I2S transmit channel */
187i2s1: &flexcomm7 {
188	status = "okay";
189	compatible = "nxp,lpc-i2s";
190	#address-cells = <1>;
191	#size-cells = <0>;
192	dmas = <&dma0 19>;
193	dma-names = "tx";
194};
195
196&sc_timer {
197	status = "okay";
198};
199
200&dma0 {
201	status = "okay";
202};
203
204&dma1 {
205	status = "okay";
206};
207