1/*
2 * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <infineon/psoc6/mpns/CYBLE_416045_02.dtsi>
10#include <infineon/psoc6/system_clocks.dtsi>
11#include "cy8cproto_063_ble-pinctrl.dtsi"
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13
14/ {
15	model = "CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit";
16	compatible = "cypress,cy8cproto_063_ble", "cypress,PSoC6";
17
18	aliases {
19		uart-5 = &uart5;
20		led0 = &user_led;
21		sw0 = &user_bt;
22		watchdog0 = &watchdog0;
23	};
24
25	chosen {
26		zephyr,sram = &sram0;
27		zephyr,flash = &flash0;
28		zephyr,console = &uart5;
29		zephyr,shell-uart = &uart5;
30	};
31
32	/delete-node/ cpu@0;
33
34	leds {
35		compatible = "gpio-leds";
36		user_led: led_0 {
37			label = "LED_0";
38			gpios = <&gpio_prt6 3 GPIO_ACTIVE_LOW>;
39		};
40	};
41
42	gpio_keys {
43		compatible = "gpio-keys";
44
45		user_bt: button_0 {
46			label = "SW_0";
47			gpios = <&gpio_prt0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
48			zephyr,code = <INPUT_KEY_0>;
49		};
50	};
51};
52
53&gpio_prt0 {
54	status = "okay";
55};
56
57&gpio_prt5 {
58	status = "okay";
59};
60
61&gpio_prt6 {
62	status = "okay";
63};
64
65&gpio_prt7 {
66	status = "okay";
67};
68
69&gpio_prt9 {
70	status = "okay";
71};
72
73&gpio_prt10 {
74	status = "okay";
75};
76
77&gpio_prt12 {
78	status = "okay";
79};
80
81uart5: &scb5 {
82	compatible = "infineon,cat1-uart";
83	status = "okay";
84	current-speed = <115200>;
85
86	/* UART pins */
87	pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>;
88	pinctrl-names = "default";
89};
90
91/* System clock configuration */
92&fll0 {
93	status = "okay";
94	clock-frequency = <100000000>;
95};
96
97&clk_hf0 {
98	clock-div = <1>;
99	clocks = <&fll0>;
100};
101
102/* CM4 core clock = 100MHz
103 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
104 */
105&clk_fast {
106	clock-div = <1>;
107};
108
109/* CM0+ core clock = 50MHz
110 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
111 */
112&clk_slow {
113	clock-div = <2>;
114};
115
116/* PERI core clock = 100MHz
117 * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz
118 */
119&clk_peri {
120	clock-div = <1>;
121};
122
123&bluetooth {
124	status = "okay";
125};
126
127&watchdog0 {
128	status = "okay";
129};
130