1# SPDX-License-Identifier: Apache-2.0
2
3zephyr_library()
4zephyr_library_sources(board.c)
5
6if((CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M1) AND (CONFIG_BUILD_OUTPUT_BIN))
7  # Generate zephyr.mem verilog memory hex dump file for initialising ITCM in
8  # Xilinx Vivado.
9  #
10  # This ought to be done using the objcopy verilog bfd, but it contains a bug
11  # affecting endianness: https://sourceware.org/bugzilla/show_bug.cgi?id=25202
12  #
13  # Instead we use bin2hex from the SiFive elf2hex package, if available.
14  # https://github.com/sifive/elf2hex
15  find_program(BIN2HEX ${CROSS_COMPILE_TARGET}-bin2hex)
16
17  if(NOT ${BIN2HEX} STREQUAL BIN2HEX-NOTFOUND)
18    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
19      COMMAND ${BIN2HEX}
20      ARGS --bit-width 32
21      ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin
22      ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.mem
23      WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
24      )
25    message(STATUS "Verilog memory hex dump will be written to: ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.mem")
26  else()
27    message(STATUS "The bin2hex (${CROSS_COMPILE_TARGET}-bin2hex) utility was not found, verilog memory hex dump file cannot be generated")
28  endif()
29endif()
30