1# x86 general configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# SPDX-License-Identifier: Apache-2.0 5 6menu "X86 Architecture Options" 7 depends on X86 8 9config ARCH 10 default "x86" 11 12# 13# CPU Families - the SoC configuration should select the right one. 14# 15 16config CPU_ATOM 17 bool 18 select CPU_HAS_FPU 19 select ARCH_HAS_STACK_PROTECTION if X86_MMU 20 select ARCH_HAS_USERSPACE if X86_MMU 21 select X86_CPU_HAS_MMX 22 select X86_CPU_HAS_SSE 23 select X86_CPU_HAS_SSE2 24 select X86_CPU_HAS_SSE3 25 select CPU_HAS_DCACHE 26 select CPU_HAS_ICACHE 27 help 28 This option signifies the use of a CPU from the Atom family. 29 30config CPU_APOLLO_LAKE 31 bool 32 select CPU_HAS_FPU 33 select ARCH_HAS_STACK_PROTECTION if X86_MMU 34 select ARCH_HAS_USERSPACE if X86_MMU 35 select X86_MMU 36 select X86_CPU_HAS_MMX 37 select X86_CPU_HAS_SSE 38 select X86_CPU_HAS_SSE2 39 select X86_CPU_HAS_SSE3 40 select X86_CPU_HAS_SSSE3 41 select X86_CPU_HAS_SSE41 42 select X86_CPU_HAS_SSE42 43 select CPU_HAS_DCACHE 44 select CPU_HAS_ICACHE 45 help 46 This option signifies the use of a CPU from the Apollo Lake family. 47 48config CPU_LAKEMONT 49 bool 50 select CPU_HAS_FPU 51 select ARCH_HAS_STACK_PROTECTION if X86_MMU 52 select ARCH_HAS_USERSPACE if X86_MMU 53 select X86_CPU_HAS_MMX 54 select X86_CPU_HAS_SSE 55 select X86_CPU_HAS_SSE2 56 select X86_CPU_HAS_SSE3 57 select X86_CPU_HAS_SSSE3 58 select CPU_HAS_DCACHE 59 select CPU_HAS_ICACHE 60 help 61 This option signifies the use of a CPU from the Lakemont family. 62 63# 64# Configuration common to both IA32 and Intel64 sub-architectures. 65# 66 67config X86_64 68 bool "Run in 64-bit mode" 69 select 64BIT 70 select USE_SWITCH 71 select USE_SWITCH_SUPPORTED 72 select SCHED_IPI_SUPPORTED 73 select X86_MMU 74 select X86_CPU_HAS_MMX 75 select X86_CPU_HAS_SSE 76 select X86_CPU_HAS_SSE2 77 select X86_MMX 78 select X86_SSE 79 select X86_SSE2 80 81menu "x86 Features" 82 83config X86_CPU_HAS_MMX 84 bool 85 86config X86_CPU_HAS_SSE 87 bool 88 89config X86_CPU_HAS_SSE2 90 bool 91 92config X86_CPU_HAS_SSE3 93 bool 94 95config X86_CPU_HAS_SSSE3 96 bool 97 98config X86_CPU_HAS_SSE41 99 bool 100 101config X86_CPU_HAS_SSE42 102 bool 103 104config X86_CPU_HAS_SSE4A 105 bool 106 107if FPU || X86_64 108 109config X86_MMX 110 bool "MMX Support" 111 depends on X86_CPU_HAS_MMX 112 help 113 This option enables MMX support, and the use of MMX registers 114 by threads. 115 116config X86_SSE 117 bool "SSE Support" 118 depends on X86_CPU_HAS_SSE 119 help 120 This option enables SSE support, and the use of SSE registers 121 by threads. 122 123config X86_SSE2 124 bool "SSE2 Support" 125 depends on X86_CPU_HAS_SSE2 126 select X86_SSE 127 help 128 This option enables SSE2 support. 129 130config X86_SSE3 131 bool "SSE3 Support" 132 depends on X86_CPU_HAS_SSE3 133 select X86_SSE 134 help 135 This option enables SSE3 support. 136 137config X86_SSSE3 138 bool "SSSE3 (Supplemental SSE3) Support" 139 depends on X86_CPU_HAS_SSSE3 140 select X86_SSE 141 help 142 This option enables Supplemental SSE3 support. 143 144config X86_SSE41 145 bool "SSE4.1 Support" 146 depends on X86_CPU_HAS_SSE41 147 select X86_SSE 148 help 149 This option enables SSE4.1 support. 150 151config X86_SSE42 152 bool "SSE4.2 Support" 153 depends on X86_CPU_HAS_SSE42 154 select X86_SSE 155 help 156 This option enables SSE4.2 support. 157 158config X86_SSE4A 159 bool "SSE4A Support" 160 depends on X86_CPU_HAS_SSE4A 161 select X86_SSE 162 help 163 This option enables SSE4A support. 164 165config X86_SSE_FP_MATH 166 bool "Compiler-generated SSEx instructions for floating point math" 167 depends on X86_SSE 168 help 169 This option allows the compiler to generate SSEx instructions for 170 performing floating point math. This can greatly improve performance 171 when exactly the same operations are to be performed on multiple 172 data objects; however, it can also significantly reduce performance 173 when preemptive task switches occur because of the larger register 174 set that must be saved and restored. 175 176 Disabling this option means that the compiler utilizes only the 177 x87 instruction set for floating point operations. 178 179endif # FPU || X86_64 180 181endmenu 182 183config SRAM_OFFSET 184 default 0x100000 if X86_PC_COMPATIBLE 185 help 186 A lot of x86 that resemble PCs have many reserved physical memory 187 regions within the first megabyte. Specify an offset from the 188 beginning of RAM to load the kernel in physical memory, avoiding these 189 regions. 190 191 Note that this does not include the "locore" which contains real mode 192 bootstrap code within the first 64K of physical memory. 193 194 This value normally need to be page-aligned. 195 196config KERNEL_VM_OFFSET 197 default 0x100000 if MMU 198 199config MAX_IRQ_LINES 200 int "Number of IRQ lines" 201 default 128 202 range 0 224 203 help 204 This option specifies the number of IRQ lines in the system. It 205 determines the size of the _irq_to_interrupt_vector_table, which 206 is used to track the association between vectors and IRQ numbers. 207 208config IRQ_OFFLOAD_VECTOR 209 int "IDT vector to use for IRQ offload" 210 default 33 211 range 32 255 212 depends on IRQ_OFFLOAD 213 214config PIC_DISABLE 215 bool "Disable PIC" 216 help 217 This option disables all interrupts on the legacy i8259 PICs at boot. 218 219choice 220 prompt "Reboot implementation" 221 depends on REBOOT 222 default REBOOT_RST_CNT 223 224 config REBOOT_RST_CNT 225 bool "Reboot via RST_CNT register" 226 help 227 Reboot via the RST_CNT register, going back to BIOS. 228endchoice 229 230config PCIE_MMIO_CFG 231 bool "Use MMIO PCI configuration space access" 232 select ACPI 233 help 234 Selects the use of the memory-mapped PCI Express Extended 235 Configuration Space instead of the traditional 0xCF8/0xCFC 236 IO Port registers. 237 238config KERNEL_VM_SIZE 239 default 0x40000000 if ACPI 240 241config X86_PC_COMPATIBLE 242 bool 243 default y 244 select ARCH_HAS_RESERVED_PAGE_FRAMES 245 select HAS_SRAM_OFFSET 246 help 247 Hidden option to signal building for PC-compatible platforms 248 with BIOS, ACPI, etc. 249 250config X86_MEMMAP 251 bool "Use memory map" 252 select ARCH_HAS_RESERVED_PAGE_FRAMES 253 help 254 Enable the use of memory map to identify regions of memory. 255 256 The memory map can be populated via Multiboot 257 (CONFIG_MULTIBOOT=y and CONFIG_MULTIBOOT_MEMMAP=y) or 258 can be manually defined via x86_memmap[]. 259 260config X86_MEMMAP_ENTRIES 261 int "Number of memory map entries" 262 depends on X86_MEMMAP 263 range 1 256 264 default 1 if !MULTIBOOT_MEMMAP 265 default 64 if MULTIBOOT_MEMMAP 266 help 267 Maximum number of memory regions to hold in the memory map. 268 269config MULTIBOOT 270 bool "Generate multiboot header" 271 depends on X86_PC_COMPATIBLE 272 default y 273 help 274 Embed a multiboot header in the output executable. This is used 275 by some boot loaders (e.g., GRUB) when loading Zephyr. It is safe 276 to leave this option on if you're not sure. It only expands the 277 text segment by 12-16 bytes and is typically ignored if not needed. 278 279if MULTIBOOT 280 281config MULTIBOOT_INFO 282 bool "Preserve multiboot information structure" 283 help 284 Multiboot passes a pointer to an information structure to the 285 kernel entry point. Some drivers (e.g., the multiboot framebuffer 286 display driver) need to refer to information in this structure, 287 and so set this option to preserve the data in a permanent location. 288 289config MULTIBOOT_MEMMAP 290 bool "Use multiboot memory map if provided" 291 select MULTIBOOT_INFO 292 select X86_MEMMAP 293 help 294 Use the multiboot memory map if the loader provides one. 295 296endif # MULTIBOOT 297 298config EXCEPTION_DEBUG 299 bool "Unhandled exception debugging" 300 default y 301 depends on LOG 302 help 303 Install handlers for various CPU exception/trap vectors to 304 make debugging them easier, at a small expense in code size. 305 This prints out the specific exception vector and any associated 306 error codes. 307 308config X86_VERY_EARLY_CONSOLE 309 bool "Support very early boot printk" 310 depends on PRINTK 311 help 312 Non-emulated X86 devices often require special hardware to attach 313 a debugger, which may not be easily available. This option adds a 314 very minimal serial driver which gets initialized at the very 315 beginning of z_cstart(), via arch_kernel_init(). This driver enables 316 printk to emit messages to the 16550 UART port 0 instance in device 317 tree. This mini-driver assumes I/O to the UART is done via ports. 318 319config X86_MMU 320 bool "Memory Management Unit" 321 select MMU 322 help 323 This options enables the memory management unit present in x86 324 and creates a set of page tables at boot time that is runtime- 325 mutable. 326 327config X86_COMMON_PAGE_TABLE 328 bool "Use a single page table for all threads" 329 default n 330 depends on USERSPACE 331 depends on !SMP 332 depends on !X86_KPTI 333 help 334 If this option is enabled, userspace memory domains will not have their 335 own page tables. Instead, context switching operations will modify 336 page tables in place. This is much slower, but uses much less RAM 337 for page tables. 338 339config X86_MAX_ADDITIONAL_MEM_DOMAINS 340 int "Maximum number of memory domains" 341 default 3 342 depends on X86_MMU && USERSPACE && !X86_COMMON_PAGE_TABLE 343 help 344 The initial page tables at boot are pre-allocated, and used for the 345 default memory domain. Instantiation of additional memory domains 346 if common page tables are in use requires a pool of free pinned 347 memory pages for constructing page tables. 348 349 Zephyr test cases assume 3 additional domains can be instantiated. 350 351config X86_EXTRA_PAGE_TABLE_PAGES 352 int "Reserve extra pages in page table" 353 default 1 if X86_PAE && (KERNEL_VM_BASE != SRAM_BASE_ADDRESS) 354 default 0 355 depends on X86_MMU 356 help 357 The whole page table is pre-allocated at build time and is 358 dependent on the range of address space. This allows reserving 359 extra pages (of size CONFIG_MMU_PAGE_SIZE) to the page table 360 so that gen_mmu.py can make use of these extra pages. 361 362 Says 0 unless absolutely sure that this is necessary. 363 364config X86_NO_MELTDOWN 365 bool 366 help 367 This hidden option should be set on a per-SOC basis to indicate that 368 a particular SOC is not vulnerable to the Meltdown CPU vulnerability, 369 as described in CVE-2017-5754. 370 371config X86_NO_SPECTRE_V1 372 bool 373 help 374 This hidden option should be set on a per-SOC basis to indicate that 375 a particular SOC is not vulnerable to the Spectre V1, V1.1, V1.2, and 376 swapgs CPU vulnerabilities as described in CVE-2017-5753, 377 CVE-2018-3693, and CVE-2019-1125. 378 379config X86_NO_SPECTRE_V2 380 bool 381 help 382 This hidden option should be set on a per-SOC basis to indicate that 383 a particular SOC is not vulnerable to the Spectre V2 CPU 384 vulnerability, as described in CVE-2017-5715. 385 386config X86_NO_SPECTRE_V4 387 bool 388 help 389 This hidden option should be set on a per-SOC basis to indicate that 390 a particular SOC is not vulnerable to the Spectre V4 CPU 391 vulnerability, as described in CVE-2018-3639. 392 393config X86_NO_LAZY_FP 394 bool 395 help 396 This hidden option should be set on a per-SOC basis to indicate 397 that a particular SOC is not vulnerable to the Lazy FP CPU 398 vulnerability, as described in CVE-2018-3665. 399 400config X86_NO_SPECULATIVE_VULNERABILITIES 401 bool 402 select X86_NO_MELTDOWN 403 select X86_NO_SPECTRE_V1 404 select X86_NO_SPECTRE_V2 405 select X86_NO_SPECTRE_V4 406 select X86_NO_LAZY_FP 407 help 408 This hidden option should be set on a per-SOC basis to indicate that 409 a particular SOC does not perform any kind of speculative execution, 410 or is a newer chip which is immune to the class of vulnerabilities 411 which exploit speculative execution side channel attacks. 412 413config DISABLE_SSBD 414 bool "Disable Speculative Store Bypass" 415 depends on USERSPACE 416 default y if !X86_NO_SPECTRE_V4 417 help 418 This option will disable Speculative Store Bypass in order to 419 mitigate against certain kinds of side channel attacks. Quoting 420 the "Speculative Execution Side Channels" document, version 2.0: 421 422 When SSBD is set, loads will not execute speculatively 423 until the addresses of all older stores are known. This 424 ensure s that a load does not speculatively consume stale 425 data values due to bypassing an older store on the same 426 logical processor. 427 428 If enabled, this applies to all threads in the system. 429 430 Even if enabled, will have no effect on CPUs that do not 431 require this feature. 432 433config ENABLE_EXTENDED_IBRS 434 bool "Extended IBRS" 435 depends on USERSPACE 436 default y if !X86_NO_SPECTRE_V2 437 help 438 This option will enable the Extended Indirect Branch Restricted 439 Speculation 'always on' feature. This mitigates Indirect Branch 440 Control vulnerabilities (aka Spectre V2). 441 442config X86_BOUNDS_CHECK_BYPASS_MITIGATION 443 bool 444 depends on USERSPACE 445 default y if !X86_NO_SPECTRE_V1 446 select BOUNDS_CHECK_BYPASS_MITIGATION 447 help 448 Hidden config to select arch-independent option to enable 449 Spectre V1 mitigations by default if the CPU is not known 450 to be immune to it. 451 452config X86_KPTI 453 bool "Kernel page table isolation" 454 default y 455 depends on USERSPACE 456 depends on !X86_NO_MELTDOWN 457 help 458 Implements kernel page table isolation to mitigate Meltdown exploits 459 to read Kernel RAM. Incurs a significant performance cost for 460 user thread interrupts and system calls, and significant footprint 461 increase for additional page tables and trampoline stacks. 462 463config X86_EFI 464 bool "EFI" 465 default y 466 depends on BUILD_OUTPUT_EFI 467 help 468 Enable EFI support. This means you build your image with zefi 469 support. See arch/x86/zefi/README.txt for more information. 470 471config X86_EFI_CONSOLE 472 bool 473 depends on X86_EFI && X86_64 && !X86_VERY_EARLY_CONSOLE 474 select EFI_CONSOLE 475 default y 476 help 477 This enables the use of the UEFI console device as the 478 Zephyr printk handler. It requires that no interferences 479 with hardware used by the firmware console (e.g. a UART or 480 framebuffer) happens from Zephyr code, and that all memory 481 used by the firmware environment and its page tables be 482 separate and preserved. In general this is safe to assume, 483 but no automatic checking exists at runtime to verify. 484 Likewise be sure to disable any other console/printk 485 drivers! 486 487source "arch/x86/core/Kconfig.ia32" 488source "arch/x86/core/Kconfig.intel64" 489 490endmenu 491
