README.txt
1SDMMC Subsystem Test
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3
4This test is designed to verify the SD subsystem stack implementation,
5and run stress tests to verify large data transfers succeed using the
6subsystem. Due to the differences between underlying SD host controller drivers,
7this test also serves as a complete test for the SDHC driver implementation in
8use. It requires an SD card be connected to the board to pass, and will
9perform destructive I/O on the card, wiping any data present. The test has
10the following phases:
11
12* Init test: verify the SD host controller can detect card presence, and
13 test the initialization flow of the SDMMC subsystem to verify that the stack
14 can correctly initialize an SD card.
15
16* IOCTL test: verify the SD subsystem correctly implements IOCTL calls required
17 for block devices in Zephyr.
18
19* Read test: verify that single block reads work, followed by multiple
20 block reads. Ensure the subsystem will reject reads beyond the end of
21 the card's stated size.
22
23* Write test: verify that single block writes work, followed by multiple
24 block writes. Ensure the subsystem will reject writes beyond the end of
25 the card's stated size.
26
27* R/W test: write data to the SD card, and verify that it is able
28 to be read back without error. Perform this R/W combination at several
29 sector locations across the SD card.
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