1# x86 general configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# SPDX-License-Identifier: Apache-2.0 5 6menu "X86 Architecture Options" 7 depends on X86 8 9config ARCH 10 default "x86" 11 12# 13# CPU Families - the SoC configuration should select the right one. 14# 15 16config CPU_ATOM 17 bool 18 select CPU_HAS_FPU 19 select ARCH_HAS_STACK_PROTECTION if X86_MMU 20 select ARCH_HAS_USERSPACE if X86_MMU 21 select X86_CPU_HAS_MMX 22 select X86_CPU_HAS_SSE 23 select X86_CPU_HAS_SSE2 24 select X86_CPU_HAS_SSE3 25 select CPU_HAS_DCACHE 26 select CPU_HAS_ICACHE 27 help 28 This option signifies the use of a CPU from the Atom family. 29 30config CPU_APOLLO_LAKE 31 bool 32 select CPU_HAS_FPU 33 select ARCH_HAS_STACK_PROTECTION if X86_MMU 34 select ARCH_HAS_USERSPACE if X86_MMU 35 select X86_MMU 36 select X86_CPU_HAS_MMX 37 select X86_CPU_HAS_SSE 38 select X86_CPU_HAS_SSE2 39 select X86_CPU_HAS_SSE3 40 select X86_CPU_HAS_SSSE3 41 select X86_CPU_HAS_SSE41 42 select X86_CPU_HAS_SSE42 43 select CPU_HAS_DCACHE 44 select CPU_HAS_ICACHE 45 help 46 This option signifies the use of a CPU from the Apollo Lake family. 47 48config CPU_LAKEMONT 49 bool 50 select CPU_HAS_FPU 51 select ARCH_HAS_STACK_PROTECTION if X86_MMU 52 select ARCH_HAS_USERSPACE if X86_MMU 53 select X86_CPU_HAS_MMX 54 select X86_CPU_HAS_SSE 55 select X86_CPU_HAS_SSE2 56 select X86_CPU_HAS_SSE3 57 select X86_CPU_HAS_SSSE3 58 select CPU_HAS_DCACHE 59 select CPU_HAS_ICACHE 60 help 61 This option signifies the use of a CPU from the Lakemont family. 62 63# 64# Configuration common to both IA32 and Intel64 sub-architectures. 65# 66 67config X86_64 68 bool "Run in 64-bit mode" 69 select 64BIT 70 select USE_SWITCH 71 select USE_SWITCH_SUPPORTED 72 select SCHED_IPI_SUPPORTED 73 select X86_MMU 74 select X86_CPU_HAS_MMX 75 select X86_CPU_HAS_SSE 76 select X86_CPU_HAS_SSE2 77 select X86_MMX 78 select X86_SSE 79 select X86_SSE2 80 81menu "x86 Features" 82 83config X86_CPU_HAS_MMX 84 bool 85 86config X86_CPU_HAS_SSE 87 bool 88 89config X86_CPU_HAS_SSE2 90 bool 91 92config X86_CPU_HAS_SSE3 93 bool 94 95config X86_CPU_HAS_SSSE3 96 bool 97 98config X86_CPU_HAS_SSE41 99 bool 100 101config X86_CPU_HAS_SSE42 102 bool 103 104config X86_CPU_HAS_SSE4A 105 bool 106 107if FPU || X86_64 108 109config X86_MMX 110 bool "MMX Support" 111 depends on X86_CPU_HAS_MMX 112 help 113 This option enables MMX support, and the use of MMX registers 114 by threads. 115 116config X86_SSE 117 bool "SSE Support" 118 depends on X86_CPU_HAS_SSE 119 help 120 This option enables SSE support, and the use of SSE registers 121 by threads. 122 123config X86_SSE2 124 bool "SSE2 Support" 125 depends on X86_CPU_HAS_SSE2 126 select X86_SSE 127 help 128 This option enables SSE2 support. 129 130config X86_SSE3 131 bool "SSE3 Support" 132 depends on X86_CPU_HAS_SSE3 133 select X86_SSE 134 help 135 This option enables SSE3 support. 136 137config X86_SSSE3 138 bool "SSSE3 (Supplemental SSE3) Support" 139 depends on X86_CPU_HAS_SSSE3 140 select X86_SSE 141 help 142 This option enables Supplemental SSE3 support. 143 144config X86_SSE41 145 bool "SSE4.1 Support" 146 depends on X86_CPU_HAS_SSE41 147 select X86_SSE 148 help 149 This option enables SSE4.1 support. 150 151config X86_SSE42 152 bool "SSE4.2 Support" 153 depends on X86_CPU_HAS_SSE42 154 select X86_SSE 155 help 156 This option enables SSE4.2 support. 157 158config X86_SSE4A 159 bool "SSE4A Support" 160 depends on X86_CPU_HAS_SSE4A 161 select X86_SSE 162 help 163 This option enables SSE4A support. 164 165config X86_SSE_FP_MATH 166 bool "Compiler-generated SSEx instructions for floating point math" 167 depends on X86_SSE 168 help 169 This option allows the compiler to generate SSEx instructions for 170 performing floating point math. This can greatly improve performance 171 when exactly the same operations are to be performed on multiple 172 data objects; however, it can also significantly reduce performance 173 when preemptive task switches occur because of the larger register 174 set that must be saved and restored. 175 176 Disabling this option means that the compiler utilizes only the 177 x87 instruction set for floating point operations. 178 179endif # FPU || X86_64 180 181endmenu 182 183config SRAM_OFFSET 184 default 0x100000 if X86_PC_COMPATIBLE 185 help 186 A lot of x86 that resemble PCs have many reserved physical memory 187 regions within the first megabyte. Specify an offset from the 188 beginning of RAM to load the kernel in physical memory, avoiding these 189 regions. 190 191 Note that this does not include the "locore" which contains real mode 192 bootstrap code within the first 64K of physical memory. 193 194 This value normally need to be page-aligned. 195 196config KERNEL_VM_OFFSET 197 default 0x100000 if MMU 198 199config MAX_IRQ_LINES 200 int "Number of IRQ lines" 201 default 128 202 range 0 224 203 help 204 This option specifies the number of IRQ lines in the system. It 205 determines the size of the _irq_to_interrupt_vector_table, which 206 is used to track the association between vectors and IRQ numbers. 207 208config IRQ_OFFLOAD_VECTOR 209 int "IDT vector to use for IRQ offload" 210 default 33 211 range 32 255 212 depends on IRQ_OFFLOAD 213 214config PIC_DISABLE 215 bool "Disable PIC" 216 help 217 This option disables all interrupts on the legacy i8259 PICs at boot. 218 219choice 220 prompt "Reboot implementation" 221 depends on REBOOT 222 default REBOOT_RST_CNT 223 224 config REBOOT_RST_CNT 225 bool "Reboot via RST_CNT register" 226 help 227 Reboot via the RST_CNT register, going back to BIOS. 228endchoice 229 230config ACPI 231 bool "ACPI (Advanced Configuration and Power Interface) support" 232 depends on X86_PC_COMPATIBLE 233 help 234 Allow retrieval of platform configuration at runtime. 235 236config PCIE_MMIO_CFG 237 bool "Use MMIO PCI configuration space access" 238 select ACPI 239 help 240 Selects the use of the memory-mapped PCI Express Extended 241 Configuration Space instead of the traditional 0xCF8/0xCFC 242 IO Port registers. 243 244config KERNEL_VM_SIZE 245 default 0x40000000 if ACPI 246 247config X86_PC_COMPATIBLE 248 bool 249 default y 250 select ARCH_HAS_RESERVED_PAGE_FRAMES 251 select HAS_SRAM_OFFSET 252 help 253 Hidden option to signal building for PC-compatible platforms 254 with BIOS, ACPI, etc. 255 256config X86_MEMMAP 257 bool "Use memory map" 258 select ARCH_HAS_RESERVED_PAGE_FRAMES 259 help 260 Enable the use of memory map to identify regions of memory. 261 262 The memory map can be populated via Multiboot 263 (CONFIG_MULTIBOOT=y and CONFIG_MULTIBOOT_MEMMAP=y) or 264 can be manually defined via x86_memmap[]. 265 266config X86_MEMMAP_ENTRIES 267 int "Number of memory map entries" 268 depends on X86_MEMMAP 269 range 1 256 270 default 1 if !MULTIBOOT_MEMMAP 271 default 64 if MULTIBOOT_MEMMAP 272 help 273 Maximum number of memory regions to hold in the memory map. 274 275config MULTIBOOT 276 bool "Generate multiboot header" 277 depends on X86_PC_COMPATIBLE 278 default y 279 help 280 Embed a multiboot header in the output executable. This is used 281 by some boot loaders (e.g., GRUB) when loading Zephyr. It is safe 282 to leave this option on if you're not sure. It only expands the 283 text segment by 12-16 bytes and is typically ignored if not needed. 284 285if MULTIBOOT 286 287config MULTIBOOT_INFO 288 bool "Preserve multiboot information structure" 289 help 290 Multiboot passes a pointer to an information structure to the 291 kernel entry point. Some drivers (e.g., the multiboot framebuffer 292 display driver) need to refer to information in this structure, 293 and so set this option to preserve the data in a permanent location. 294 295config MULTIBOOT_MEMMAP 296 bool "Use multiboot memory map if provided" 297 select MULTIBOOT_INFO 298 select X86_MEMMAP 299 help 300 Use the multiboot memory map if the loader provides one. 301 302endif # MULTIBOOT 303 304config EXCEPTION_DEBUG 305 bool "Unhandled exception debugging" 306 default y 307 depends on LOG 308 help 309 Install handlers for various CPU exception/trap vectors to 310 make debugging them easier, at a small expense in code size. 311 This prints out the specific exception vector and any associated 312 error codes. 313 314config X86_VERY_EARLY_CONSOLE 315 bool "Support very early boot printk" 316 depends on PRINTK 317 help 318 Non-emulated X86 devices often require special hardware to attach 319 a debugger, which may not be easily available. This option adds a 320 very minimal serial driver which gets initialized at the very 321 beginning of z_cstart(), via arch_kernel_init(). This driver enables 322 printk to emit messages to the 16550 UART port 0 instance in device 323 tree. This mini-driver assumes I/O to the UART is done via ports. 324 325config X86_MMU 326 bool "Memory Management Unit" 327 select MMU 328 help 329 This options enables the memory management unit present in x86 330 and creates a set of page tables at boot time that is runtime- 331 mutable. 332 333config X86_COMMON_PAGE_TABLE 334 bool "Use a single page table for all threads" 335 default n 336 depends on USERSPACE 337 depends on !SMP 338 depends on !X86_KPTI 339 help 340 If this option is enabled, userspace memory domains will not have their 341 own page tables. Instead, context switching operations will modify 342 page tables in place. This is much slower, but uses much less RAM 343 for page tables. 344 345config X86_MAX_ADDITIONAL_MEM_DOMAINS 346 int "Maximum number of memory domains" 347 default 3 348 depends on X86_MMU && USERSPACE && !X86_COMMON_PAGE_TABLE 349 help 350 The initial page tables at boot are pre-allocated, and used for the 351 default memory domain. Instantiation of additional memory domains 352 if common page tables are in use requires a pool of free pinned 353 memory pages for constructing page tables. 354 355 Zephyr test cases assume 3 additional domains can be instantiated. 356 357config X86_EXTRA_PAGE_TABLE_PAGES 358 int "Reserve extra pages in page table" 359 default 1 if X86_PAE && (KERNEL_VM_BASE != SRAM_BASE_ADDRESS) 360 default 0 361 depends on X86_MMU 362 help 363 The whole page table is pre-allocated at build time and is 364 dependent on the range of address space. This allows reserving 365 extra pages (of size CONFIG_MMU_PAGE_SIZE) to the page table 366 so that gen_mmu.py can make use of these extra pages. 367 368 Says 0 unless absolutely sure that this is necessary. 369 370config X86_NO_MELTDOWN 371 bool 372 help 373 This hidden option should be set on a per-SOC basis to indicate that 374 a particular SOC is not vulnerable to the Meltdown CPU vulnerability, 375 as described in CVE-2017-5754. 376 377config X86_NO_SPECTRE_V1 378 bool 379 help 380 This hidden option should be set on a per-SOC basis to indicate that 381 a particular SOC is not vulnerable to the Spectre V1, V1.1, V1.2, and 382 swapgs CPU vulnerabilities as described in CVE-2017-5753, 383 CVE-2018-3693, and CVE-2019-1125. 384 385config X86_NO_SPECTRE_V2 386 bool 387 help 388 This hidden option should be set on a per-SOC basis to indicate that 389 a particular SOC is not vulnerable to the Spectre V2 CPU 390 vulnerability, as described in CVE-2017-5715. 391 392config X86_NO_SPECTRE_V4 393 bool 394 help 395 This hidden option should be set on a per-SOC basis to indicate that 396 a particular SOC is not vulnerable to the Spectre V4 CPU 397 vulnerability, as described in CVE-2018-3639. 398 399config X86_NO_LAZY_FP 400 bool 401 help 402 This hidden option should be set on a per-SOC basis to indicate 403 that a particular SOC is not vulnerable to the Lazy FP CPU 404 vulnerability, as described in CVE-2018-3665. 405 406config X86_NO_SPECULATIVE_VULNERABILITIES 407 bool 408 select X86_NO_MELTDOWN 409 select X86_NO_SPECTRE_V1 410 select X86_NO_SPECTRE_V2 411 select X86_NO_SPECTRE_V4 412 select X86_NO_LAZY_FP 413 help 414 This hidden option should be set on a per-SOC basis to indicate that 415 a particular SOC does not perform any kind of speculative execution, 416 or is a newer chip which is immune to the class of vulnerabilities 417 which exploit speculative execution side channel attacks. 418 419config DISABLE_SSBD 420 bool "Disable Speculative Store Bypass" 421 depends on USERSPACE 422 default y if !X86_NO_SPECTRE_V4 423 help 424 This option will disable Speculative Store Bypass in order to 425 mitigate against certain kinds of side channel attacks. Quoting 426 the "Speculative Execution Side Channels" document, version 2.0: 427 428 When SSBD is set, loads will not execute speculatively 429 until the addresses of all older stores are known. This 430 ensure s that a load does not speculatively consume stale 431 data values due to bypassing an older store on the same 432 logical processor. 433 434 If enabled, this applies to all threads in the system. 435 436 Even if enabled, will have no effect on CPUs that do not 437 require this feature. 438 439config ENABLE_EXTENDED_IBRS 440 bool "Extended IBRS" 441 depends on USERSPACE 442 default y if !X86_NO_SPECTRE_V2 443 help 444 This option will enable the Extended Indirect Branch Restricted 445 Speculation 'always on' feature. This mitigates Indirect Branch 446 Control vulnerabilities (aka Spectre V2). 447 448config X86_BOUNDS_CHECK_BYPASS_MITIGATION 449 bool 450 depends on USERSPACE 451 default y if !X86_NO_SPECTRE_V1 452 select BOUNDS_CHECK_BYPASS_MITIGATION 453 help 454 Hidden config to select arch-independent option to enable 455 Spectre V1 mitigations by default if the CPU is not known 456 to be immune to it. 457 458config X86_KPTI 459 bool "Kernel page table isolation" 460 default y 461 depends on USERSPACE 462 depends on !X86_NO_MELTDOWN 463 help 464 Implements kernel page table isolation to mitigate Meltdown exploits 465 to read Kernel RAM. Incurs a significant performance cost for 466 user thread interrupts and system calls, and significant footprint 467 increase for additional page tables and trampoline stacks. 468 469config X86_EFI 470 bool "EFI" 471 default y 472 depends on BUILD_OUTPUT_EFI 473 help 474 Enable EFI support. This means you build your image with zefi 475 support. See arch/x86/zefi/README.txt for more information. 476 477config X86_EFI_CONSOLE 478 bool 479 depends on X86_EFI && X86_64 && !X86_VERY_EARLY_CONSOLE 480 select EFI_CONSOLE 481 default y 482 help 483 This enables the use of the UEFI console device as the 484 Zephyr printk handler. It requires that no interferences 485 with hardware used by the firmware console (e.g. a UART or 486 framebuffer) happens from Zephyr code, and that all memory 487 used by the firmware environment and its page tables be 488 separate and preserved. In general this is safe to assume, 489 but no automatic checking exists at runtime to verify. 490 Likewise be sure to disable any other console/printk 491 drivers! 492 493source "arch/x86/core/Kconfig.ia32" 494source "arch/x86/core/Kconfig.intel64" 495 496endmenu 497
