1/*
2 * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <freq.h>
8#include <mem.h>
9#include <wch/qingke-v4c.dtsi>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h>
13
14/ {
15	clocks {
16		clk_hse: clk-hse {
17			#clock-cells = <0>;
18			compatible = "wch,ch32v00x-hse-clock";
19			clock-frequency = <DT_FREQ_M(32)>;
20			status = "disabled";
21		};
22
23		clk_hsi: clk-hsi {
24			#clock-cells = <0>;
25			compatible = "wch,ch32v00x-hsi-clock";
26			clock-frequency = <DT_FREQ_M(8)>;
27			status = "disabled";
28		};
29
30		clk_lsi: clk-lsi {
31			#clock-cells = <0>;
32			compatible = "fixed-clock";
33			clock-frequency = <DT_FREQ_K(32)>;
34			status = "disabled";
35		};
36
37		pll: pll {
38			#clock-cells = <0>;
39			compatible = "wch,ch32v20x_30x-pll-clock";
40			mul = <18>;
41			status = "disabled";
42		};
43	};
44
45	soc {
46		sram0: memory@20000000 {
47			compatible = "mmio-sram";
48			reg = <0x20000000 DT_SIZE_K(64)>;
49		};
50
51		flash: flash-controller@40022000 {
52			compatible = "wch,ch32v20x_30x-flash-controller";
53			reg = <0x40022000 0x400>;
54			#address-cells = <1>;
55			#size-cells = <1>;
56
57			flash0: flash@0 {
58				compatible = "soc-nv-flash";
59				reg = <0 DT_SIZE_K(128)>;
60			};
61		};
62
63		pwr: pwr@40007000 {
64			compatible = "wch,pwr";
65			reg = <0x40007000 16>;
66		};
67
68		pinctrl: pin-controller@40010000 {
69			compatible = "wch,20x_30x-afio";
70			reg = <0x40010000 16>;
71			#address-cells = <1>;
72			#size-cells = <1>;
73
74			gpioa: gpio@40010800 {
75				compatible = "wch,gpio";
76				reg = <0x40010800 0x20>;
77				gpio-controller;
78				#gpio-cells = <2>;
79				ngpios = <8>;
80				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>;
81			};
82
83			gpiob: gpio@40010C00 {
84				compatible = "wch,gpio";
85				reg = <0x40010C00 0x20>;
86				gpio-controller;
87				#gpio-cells = <2>;
88				ngpios = <8>;
89				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>;
90			};
91
92			gpioc: gpio@40011000 {
93				compatible = "wch,gpio";
94				reg = <0x40011000 0x20>;
95				gpio-controller;
96				#gpio-cells = <2>;
97				ngpios = <8>;
98				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>;
99			};
100
101			gpiod: gpio@40011400 {
102				compatible = "wch,gpio";
103				reg = <0x40011400 0x20>;
104				gpio-controller;
105				#gpio-cells = <2>;
106				ngpios = <8>;
107				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>;
108			};
109		};
110
111		usart1: uart@40013800 {
112			compatible = "wch,usart";
113			reg = <0x40013800 0x20>;
114			clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>;
115			interrupt-parent = <&pfic>;
116			interrupts = <53>;
117			status = "disabled";
118		};
119
120		usart2: uart@40004400 {
121			compatible = "wch,usart";
122			reg = <0x40004400 0x20>;
123			clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>;
124			interrupt-parent = <&pfic>;
125			interrupts = <54>;
126			status = "disabled";
127		};
128
129		usart3: uart@40004800 {
130			compatible = "wch,usart";
131			reg = <0x40004800 0x20>;
132			clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>;
133			interrupt-parent = <&pfic>;
134			interrupts = <55>;
135			status = "disabled";
136		};
137
138		usart4: uart@40004c00 {
139			compatible = "wch,usart";
140			reg = <0x40004C00 0x20>;
141			clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>;
142			interrupt-parent = <&pfic>;
143			interrupts = <68>;
144			status = "disabled";
145		};
146
147		rcc: rcc@40021000 {
148			compatible = "wch,rcc";
149			reg = <0x40021000 16>;
150			#clock-cells = <1>;
151		};
152	};
153};
154
155&cpu0 {
156	clock-frequency = <DT_FREQ_M(144)>;
157};
158