1/* 2 * Copyright (c) 2021 The Chromium OS Authors 3 * Copyright (c) 2021 Linaro Limited 4 * Copyright (c) 2023 PSICONTROL nv 5 * Copyright (c) 2024 STMicroelectronics 6 * 7 * SPDX-License-Identifier: Apache-2.0 8 */ 9 10 11#include <arm/armv8-m.dtsi> 12#include <zephyr/dt-bindings/adc/adc.h> 13#include <zephyr/dt-bindings/pwm/pwm.h> 14#include <zephyr/dt-bindings/clock/stm32u5_clock.h> 15#include <zephyr/dt-bindings/gpio/gpio.h> 16#include <zephyr/dt-bindings/i2c/i2c.h> 17#include <zephyr/dt-bindings/flash_controller/ospi.h> 18#include <zephyr/dt-bindings/reset/stm32u5_reset.h> 19#include <zephyr/dt-bindings/dma/stm32_dma.h> 20#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h> 21#include <zephyr/dt-bindings/adc/stm32u5_adc.h> 22#include <zephyr/dt-bindings/power/stm32_pwr.h> 23#include <freq.h> 24 25/ { 26 chosen { 27 zephyr,entropy = &rng; 28 zephyr,flash-controller = &flash; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-m33"; 38 reg = <0>; 39 #address-cells = <1>; 40 #size-cells = <1>; 41 cpu-power-states = <&stop0 &stop1 &stop2>; 42 43 mpu: mpu@e000ed90 { 44 compatible = "arm,armv8m-mpu"; 45 reg = <0xe000ed90 0x40>; 46 }; 47 }; 48 49 power-states { 50 stop0: state0 { 51 compatible = "zephyr,power-state"; 52 power-state-name = "suspend-to-idle"; 53 substate-id = <1>; 54 min-residency-us = <100>; 55 }; 56 stop1: state1 { 57 compatible = "zephyr,power-state"; 58 power-state-name = "suspend-to-idle"; 59 substate-id = <2>; 60 min-residency-us = <500>; 61 }; 62 stop2: state2 { 63 compatible = "zephyr,power-state"; 64 power-state-name = "suspend-to-idle"; 65 substate-id = <3>; 66 min-residency-us = <900>; 67 }; 68 /omit-if-no-ref/ stop3: state3 { 69 compatible = "zephyr,power-state"; 70 power-state-name = "suspend-to-idle"; 71 substate-id = <4>; 72 min-residency-us = <200000>; 73 exit-latency-us = <130>; 74 }; 75 }; 76 }; 77 78 sram0: memory@20000000 { 79 compatible = "mmio-sram"; 80 }; 81 82 clocks { 83 clk_hse: clk-hse { 84 #clock-cells = <0>; 85 compatible = "st,stm32-hse-clock"; 86 status = "disabled"; 87 }; 88 89 clk_hsi: clk-hsi { 90 #clock-cells = <0>; 91 compatible = "fixed-clock"; 92 clock-frequency = <DT_FREQ_M(16)>; 93 status = "disabled"; 94 }; 95 96 clk_hsi48: clk-hsi48 { 97 #clock-cells = <0>; 98 compatible = "fixed-clock"; 99 clock-frequency = <DT_FREQ_M(48)>; 100 status = "disabled"; 101 }; 102 103 clk_msis: clk-msis { 104 #clock-cells = <0>; 105 compatible = "st,stm32u5-msi-clock"; 106 msi-range = <4>; /* 4MHz (reset value) */ 107 status = "disabled"; 108 }; 109 110 clk_msik: clk-msik { 111 #clock-cells = <0>; 112 compatible = "st,stm32u5-msi-clock"; 113 msi-range = <4>; /* 4MHz (reset value) */ 114 status = "disabled"; 115 }; 116 117 clk_lse: clk-lse { 118 #clock-cells = <0>; 119 compatible = "st,stm32-lse-clock"; 120 clock-frequency = <32768>; 121 driving-capability = <2>; 122 status = "disabled"; 123 }; 124 125 clk_lsi: clk-lsi { 126 #clock-cells = <0>; 127 compatible = "fixed-clock"; 128 clock-frequency = <DT_FREQ_K(32)>; 129 status = "disabled"; 130 }; 131 132 pll1: pll: pll { 133 #clock-cells = <0>; 134 compatible = "st,stm32u5-pll-clock"; 135 status = "disabled"; 136 }; 137 138 pll2: pll2 { 139 #clock-cells = <0>; 140 compatible = "st,stm32u5-pll-clock"; 141 status = "disabled"; 142 }; 143 144 pll3: pll3 { 145 #clock-cells = <0>; 146 compatible = "st,stm32u5-pll-clock"; 147 status = "disabled"; 148 }; 149 }; 150 151 mcos { 152 mco1: mco1 { 153 compatible = "st,stm32-clock-mco"; 154 status = "disabled"; 155 }; 156 }; 157 158 soc { 159 flash: flash-controller@40022000 { 160 compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller"; 161 reg = <0x40022000 0x400>; 162 interrupts = <6 0>; 163 164 #address-cells = <1>; 165 #size-cells = <1>; 166 167 flash0: flash@8000000 { 168 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 169 170 write-block-size = <16>; 171 erase-block-size = <8192>; 172 /* maximum erase time(ms) for a 8K sector */ 173 max-erase-time = <5>; 174 }; 175 }; 176 177 rcc: rcc@46020c00 { 178 compatible = "st,stm32u5-rcc"; 179 clocks-controller; 180 #clock-cells = <2>; 181 reg = <0x46020c00 0x400>; 182 183 rctl: reset-controller { 184 compatible = "st,stm32-rcc-rctl"; 185 #reset-cells = <1>; 186 }; 187 }; 188 189 exti: interrupt-controller@46022000 { 190 compatible = "st,stm32g0-exti", "st,stm32-exti"; 191 interrupt-controller; 192 #interrupt-cells = <1>; 193 #address-cells = <1>; 194 reg = <0x46022000 0x400>; 195 num-lines = <16>; 196 interrupts = <11 0>, <12 0>, <13 0>, <14 0>, 197 <15 0>, <16 0>, <17 0>, <18 0>, 198 <19 0>, <20 0>, <21 0>, <22 0>, 199 <23 0>, <24 0>, <25 0>, <26 0>; 200 interrupt-names = "line0", "line1", "line2", "line3", 201 "line4", "line5", "line6", "line7", 202 "line8", "line9", "line10", "line11", 203 "line12", "line13", "line14", "line15"; 204 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 205 <4 1>, <5 1>, <6 1>, <7 1>, 206 <8 1>, <9 1>, <10 1>, <11 1>, 207 <12 1>, <13 1>, <14 1>, <15 1>; 208 }; 209 210 pinctrl: pin-controller@42020000 { 211 compatible = "st,stm32-pinctrl"; 212 #address-cells = <1>; 213 #size-cells = <1>; 214 reg = <0x42020000 0x2000>; 215 216 gpioa: gpio@42020000 { 217 compatible = "st,stm32-gpio"; 218 gpio-controller; 219 #gpio-cells = <2>; 220 reg = <0x42020000 0x400>; 221 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; 222 }; 223 224 gpiob: gpio@42020400 { 225 compatible = "st,stm32-gpio"; 226 gpio-controller; 227 #gpio-cells = <2>; 228 reg = <0x42020400 0x400>; 229 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; 230 }; 231 232 gpioc: gpio@42020800 { 233 compatible = "st,stm32-gpio"; 234 gpio-controller; 235 #gpio-cells = <2>; 236 reg = <0x42020800 0x400>; 237 clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; 238 }; 239 240 gpiod: gpio@42020c00 { 241 compatible = "st,stm32-gpio"; 242 gpio-controller; 243 #gpio-cells = <2>; 244 reg = <0x42020c00 0x400>; 245 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; 246 }; 247 248 gpioe: gpio@42021000 { 249 compatible = "st,stm32-gpio"; 250 gpio-controller; 251 #gpio-cells = <2>; 252 reg = <0x42021000 0x400>; 253 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; 254 }; 255 256 gpiof: gpio@42021400 { 257 compatible = "st,stm32-gpio"; 258 gpio-controller; 259 #gpio-cells = <2>; 260 reg = <0x42021400 0x400>; 261 clocks = <&rcc STM32_CLOCK(AHB2, 5U)>; 262 }; 263 264 gpiog: gpio@42021800 { 265 compatible = "st,stm32-gpio"; 266 gpio-controller; 267 #gpio-cells = <2>; 268 reg = <0x42021800 0x400>; 269 clocks = <&rcc STM32_CLOCK(AHB2, 6U)>; 270 }; 271 272 gpioh: gpio@42021c00 { 273 compatible = "st,stm32-gpio"; 274 gpio-controller; 275 #gpio-cells = <2>; 276 reg = <0x42021c00 0x400>; 277 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; 278 }; 279 280 gpioi: gpio@42022000 { 281 compatible = "st,stm32-gpio"; 282 gpio-controller; 283 #gpio-cells = <2>; 284 reg = <0x42022000 0x400>; 285 clocks = <&rcc STM32_CLOCK(AHB2, 8U)>; 286 }; 287 }; 288 289 iwdg: watchdog@40003000 { 290 compatible = "st,stm32-watchdog"; 291 reg = <0x40003000 0x400>; 292 status = "disabled"; 293 }; 294 295 wwdg: wwdg1: watchdog@40002c00 { 296 compatible = "st,stm32-window-watchdog"; 297 reg = <0x40002c00 0x1000>; 298 clocks = <&rcc STM32_CLOCK(APB1, 11U)>; 299 interrupts = <0 7>; 300 status = "disabled"; 301 }; 302 303 backup_sram: memory@40036400 { 304 compatible = "zephyr,memory-region", "st,stm32-backup-sram"; 305 reg = <0x40036400 DT_SIZE_K(2)>; 306 /* BKPSRAMEN and RAMCFGEN clock enable */ 307 clocks = <&rcc STM32_CLOCK(AHB1, 28U)>; 308 zephyr,memory-region = "BACKUP_SRAM"; 309 status = "disabled"; 310 }; 311 312 usart1: serial@40013800 { 313 compatible = "st,stm32-usart", "st,stm32-uart"; 314 reg = <0x40013800 0x400>; 315 clocks = <&rcc STM32_CLOCK(APB2, 14U)>; 316 resets = <&rctl STM32_RESET(APB2, 14U)>; 317 interrupts = <61 0>; 318 status = "disabled"; 319 }; 320 321 usart2: serial@40004400 { 322 compatible = "st,stm32-usart", "st,stm32-uart"; 323 reg = <0x40004400 0x400>; 324 clocks = <&rcc STM32_CLOCK(APB1, 17U)>; 325 resets = <&rctl STM32_RESET(APB1L, 17U)>; 326 interrupts = <62 0>; 327 status = "disabled"; 328 }; 329 330 usart3: serial@40004800 { 331 compatible = "st,stm32-usart", "st,stm32-uart"; 332 reg = <0x40004800 0x400>; 333 clocks = <&rcc STM32_CLOCK(APB1, 18U)>; 334 resets = <&rctl STM32_RESET(APB1L, 18U)>; 335 interrupts = <63 0>; 336 status = "disabled"; 337 }; 338 339 uart4: serial@40004c00 { 340 compatible = "st,stm32-uart"; 341 reg = <0x40004c00 0x400>; 342 clocks = <&rcc STM32_CLOCK(APB1, 19U)>; 343 resets = <&rctl STM32_RESET(APB1L, 19U)>; 344 interrupts = <64 0>; 345 status = "disabled"; 346 }; 347 348 uart5: serial@40005000 { 349 compatible = "st,stm32-uart"; 350 reg = <0x40005000 0x400>; 351 clocks = <&rcc STM32_CLOCK(APB1, 20U)>; 352 resets = <&rctl STM32_RESET(APB1L, 20U)>; 353 interrupts = <65 0>; 354 status = "disabled"; 355 }; 356 357 lpuart1: serial@46002400 { 358 compatible = "st,stm32-lpuart", "st,stm32-uart"; 359 reg = <0x46002400 0x400>; 360 clocks = <&rcc STM32_CLOCK(APB3, 6U)>; 361 resets = <&rctl STM32_RESET(APB3, 6U)>; 362 interrupts = <66 0>; 363 status = "disabled"; 364 }; 365 366 spi1: spi@40013000 { 367 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 reg = <0x40013000 0x400>; 371 interrupts = <59 5>; 372 clocks = <&rcc STM32_CLOCK(APB2, 12U)>; 373 status = "disabled"; 374 }; 375 376 spi2: spi@40003800 { 377 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 reg = <0x40003800 0x400>; 381 interrupts = <60 5>; 382 clocks = <&rcc STM32_CLOCK(APB1, 14U)>; 383 status = "disabled"; 384 }; 385 386 spi3: spi@46002000 { 387 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 reg = <0x46002000 0x400>; 391 interrupts = <99 5>; 392 clocks = <&rcc STM32_CLOCK(APB3, 5U)>; 393 status = "disabled"; 394 }; 395 396 i2c1: i2c@40005400 { 397 compatible = "st,stm32-i2c-v2"; 398 clock-frequency = <I2C_BITRATE_STANDARD>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 reg = <0x40005400 0x400>; 402 clocks = <&rcc STM32_CLOCK(APB1, 21U)>; 403 interrupts = <55 0>, <56 0>; 404 interrupt-names = "event", "error"; 405 status = "disabled"; 406 }; 407 408 i2c2: i2c@40005800 { 409 compatible = "st,stm32-i2c-v2"; 410 clock-frequency = <I2C_BITRATE_STANDARD>; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 reg = <0x40005800 0x400>; 414 clocks = <&rcc STM32_CLOCK(APB1, 22U)>; 415 interrupts = <57 0>, <58 0>; 416 interrupt-names = "event", "error"; 417 status = "disabled"; 418 }; 419 420 i2c3: i2c@46002800 { 421 compatible = "st,stm32-i2c-v2"; 422 clock-frequency = <I2C_BITRATE_STANDARD>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 reg = <0x46002800 0x400>; 426 clocks = <&rcc STM32_CLOCK(APB3, 7U)>; 427 interrupts = <88 0>, <89 0>; 428 interrupt-names = "event", "error"; 429 status = "disabled"; 430 }; 431 432 i2c4: i2c@40008400 { 433 compatible = "st,stm32-i2c-v2"; 434 clock-frequency = <I2C_BITRATE_STANDARD>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 reg = <0x40008400 0x400>; 438 clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>; 439 interrupts = <101 0>, <100 0>; 440 interrupt-names = "event", "error"; 441 status = "disabled"; 442 }; 443 444 lptim1: timers@46004400 { 445 compatible = "st,stm32-lptim"; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 reg = <0x46004400 0x400>; 449 clocks = <&rcc STM32_CLOCK(APB3, 11U)>; 450 interrupts = <67 1>; 451 interrupt-names = "wakeup"; 452 status = "disabled"; 453 }; 454 455 lptim2: timers@40009400 { 456 compatible = "st,stm32-lptim"; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 reg = <0x40009400 0x400>; 460 clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>; 461 interrupts = <68 0>; 462 interrupt-names = "global"; 463 status = "disabled"; 464 }; 465 466 lptim3: timers@46004800 { 467 compatible = "st,stm32-lptim"; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 reg = <0x46004800 0x400>; 471 clocks = <&rcc STM32_CLOCK(APB3, 12U)>; 472 interrupts = <98 0>; 473 interrupt-names = "global"; 474 status = "disabled"; 475 }; 476 477 lptim4: timers@46004c00 { 478 compatible = "st,stm32-lptim"; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 reg = <0x46004c00 0x400>; 482 clocks = <&rcc STM32_CLOCK(APB3, 13U)>; 483 interrupts = <110 0>; 484 interrupt-names = "global"; 485 status = "disabled"; 486 }; 487 488 rtc: rtc@46007800 { 489 compatible = "st,stm32-rtc"; 490 reg = <0x46007800 0x400>; 491 interrupts = <2 0>; 492 clocks = <&rcc STM32_CLOCK(APB3, 21U)>; 493 prescaler = <32768>; 494 alarms-count = <2>; 495 status = "disabled"; 496 }; 497 498 timers1: timers@40012c00 { 499 compatible = "st,stm32-timers"; 500 reg = <0x40012c00 0x400>; 501 clocks = <&rcc STM32_CLOCK(APB2, 11U)>; 502 resets = <&rctl STM32_RESET(APB2, 11U)>; 503 interrupts = <41 0>, <42 0>, <43 0>, <44 0>; 504 interrupt-names = "brk", "up", "trgcom", "cc"; 505 status = "disabled"; 506 507 pwm { 508 compatible = "st,stm32-pwm"; 509 status = "disabled"; 510 #pwm-cells = <3>; 511 }; 512 }; 513 514 timers2: timers@40000000 { 515 compatible = "st,stm32-timers"; 516 reg = <0x40000000 0x400>; 517 clocks = <&rcc STM32_CLOCK(APB1, 0U)>; 518 resets = <&rctl STM32_RESET(APB1L, 0U)>; 519 interrupts = <45 0>; 520 interrupt-names = "global"; 521 status = "disabled"; 522 523 pwm { 524 compatible = "st,stm32-pwm"; 525 status = "disabled"; 526 #pwm-cells = <3>; 527 }; 528 }; 529 530 timers3: timers@40000400 { 531 compatible = "st,stm32-timers"; 532 reg = <0x40000400 0x400>; 533 clocks = <&rcc STM32_CLOCK(APB1, 1U)>; 534 resets = <&rctl STM32_RESET(APB1L, 1U)>; 535 interrupts = <46 0>; 536 interrupt-names = "global"; 537 status = "disabled"; 538 539 pwm { 540 compatible = "st,stm32-pwm"; 541 status = "disabled"; 542 #pwm-cells = <3>; 543 }; 544 }; 545 546 timers4: timers@40000800 { 547 compatible = "st,stm32-timers"; 548 reg = <0x40000800 0x400>; 549 clocks = <&rcc STM32_CLOCK(APB1, 2U)>; 550 resets = <&rctl STM32_RESET(APB1L, 2U)>; 551 interrupts = <47 0>; 552 interrupt-names = "global"; 553 status = "disabled"; 554 555 pwm { 556 compatible = "st,stm32-pwm"; 557 status = "disabled"; 558 #pwm-cells = <3>; 559 }; 560 561 counter { 562 compatible = "st,stm32-counter"; 563 status = "disabled"; 564 }; 565 }; 566 567 timers5: timers@40000c00 { 568 compatible = "st,stm32-timers"; 569 reg = <0x40000c00 0x400>; 570 clocks = <&rcc STM32_CLOCK(APB1, 3U)>; 571 resets = <&rctl STM32_RESET(APB1L, 3U)>; 572 interrupts = <48 0>; 573 interrupt-names = "global"; 574 status = "disabled"; 575 576 pwm { 577 compatible = "st,stm32-pwm"; 578 status = "disabled"; 579 #pwm-cells = <3>; 580 }; 581 582 counter { 583 compatible = "st,stm32-counter"; 584 status = "disabled"; 585 }; 586 }; 587 588 timers6: timers@40001000 { 589 compatible = "st,stm32-timers"; 590 reg = <0x40001000 0x400>; 591 clocks = <&rcc STM32_CLOCK(APB1, 4U)>; 592 resets = <&rctl STM32_RESET(APB1L, 4U)>; 593 interrupts = <49 0>; 594 interrupt-names = "global"; 595 status = "disabled"; 596 597 pwm { 598 compatible = "st,stm32-pwm"; 599 status = "disabled"; 600 #pwm-cells = <3>; 601 }; 602 }; 603 604 timers7: timers@40001400 { 605 compatible = "st,stm32-timers"; 606 reg = <0x40001400 0x400>; 607 clocks = <&rcc STM32_CLOCK(APB1, 5U)>; 608 resets = <&rctl STM32_RESET(APB1L, 5U)>; 609 interrupts = <50 0>; 610 interrupt-names = "global"; 611 status = "disabled"; 612 613 pwm { 614 compatible = "st,stm32-pwm"; 615 status = "disabled"; 616 #pwm-cells = <3>; 617 }; 618 }; 619 620 timers8: timers@40013400 { 621 compatible = "st,stm32-timers"; 622 reg = <0x40013400 0x400>; 623 clocks = <&rcc STM32_CLOCK(APB2, 13U)>; 624 resets = <&rctl STM32_RESET(APB2, 13U)>; 625 interrupts = <51 0>, <52 0>, <53 0>, <54 0>; 626 interrupt-names = "brk", "up", "trgcom", "cc"; 627 status = "disabled"; 628 629 pwm { 630 compatible = "st,stm32-pwm"; 631 status = "disabled"; 632 #pwm-cells = <3>; 633 }; 634 }; 635 636 timers15: timers@40014000 { 637 compatible = "st,stm32-timers"; 638 reg = <0x40014000 0x400>; 639 clocks = <&rcc STM32_CLOCK(APB2, 16U)>; 640 resets = <&rctl STM32_RESET(APB2, 16U)>; 641 interrupts = <69 0>; 642 interrupt-names = "global"; 643 status = "disabled"; 644 645 pwm { 646 compatible = "st,stm32-pwm"; 647 status = "disabled"; 648 #pwm-cells = <3>; 649 }; 650 651 counter { 652 compatible = "st,stm32-counter"; 653 status = "disabled"; 654 }; 655 }; 656 657 timers16: timers@40014400 { 658 compatible = "st,stm32-timers"; 659 reg = <0x40014400 0x400>; 660 clocks = <&rcc STM32_CLOCK(APB2, 17U)>; 661 resets = <&rctl STM32_RESET(APB2, 17U)>; 662 interrupts = <70 0>; 663 interrupt-names = "global"; 664 status = "disabled"; 665 666 pwm { 667 compatible = "st,stm32-pwm"; 668 status = "disabled"; 669 #pwm-cells = <3>; 670 }; 671 672 counter { 673 compatible = "st,stm32-counter"; 674 status = "disabled"; 675 }; 676 }; 677 678 timers17: timers@40014800 { 679 compatible = "st,stm32-timers"; 680 reg = <0x40014800 0x400>; 681 clocks = <&rcc STM32_CLOCK(APB2, 18U)>; 682 resets = <&rctl STM32_RESET(APB2, 18U)>; 683 interrupts = <71 0>; 684 interrupt-names = "global"; 685 status = "disabled"; 686 687 pwm { 688 compatible = "st,stm32-pwm"; 689 status = "disabled"; 690 #pwm-cells = <3>; 691 }; 692 693 counter { 694 compatible = "st,stm32-counter"; 695 status = "disabled"; 696 }; 697 }; 698 699 octospi1: octospi@420d1400 { 700 compatible = "st,stm32-ospi"; 701 reg = <0x420d1400 0x400>; 702 interrupts = <76 0>; 703 clock-names = "ospix", "ospi-ker", "ospi-mgr"; 704 clocks = <&rcc STM32_CLOCK(AHB2_2, 4U)>, 705 <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>, 706 <&rcc STM32_CLOCK(AHB2, 21U)>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 status = "disabled"; 710 }; 711 712 octospi2: octospi@420d2400 { 713 compatible = "st,stm32-ospi"; 714 reg = <0x420d2400 0x400>; 715 interrupts = <120 0>; 716 clock-names = "ospix", "ospi-ker", "ospi-mgr"; 717 clocks = <&rcc STM32_CLOCK(AHB2_2, 8U)>, 718 <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>, 719 <&rcc STM32_CLOCK(AHB2, 21U)>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 status = "disabled"; 723 }; 724 725 aes: aes@420c0000 { 726 compatible = "st,stm32-aes"; 727 reg = <0x420c0000 0x400>; 728 clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; 729 resets = <&rctl STM32_RESET(AHB2L, 16U)>; 730 interrupts = <93 0>; 731 status = "disabled"; 732 }; 733 734 rng: rng@420c0800 { 735 compatible = "st,stm32-rng"; 736 reg = <0x420c0800 0x400>; 737 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>; 738 interrupts = <94 0>; 739 nist-config = <0xf60d00>; 740 health-test-config = <0x9aae>; 741 status = "disabled"; 742 }; 743 744 /* 745 * The SDMMC domain clock can be chosen between ICLK and PLL1P. 746 * But ICLK is itself chosen among HSI48 (the default), PLL2Q, 747 * PLL1Q and MSIK. 748 * 749 * Currently, configuring ICLK is unsupported. When support for 750 * ICLK comes in the future, the clock source for sdmmc1 and 751 * sdmmc2 will have to be replaced with STM32_SRC_ICLK. 752 */ 753 sdmmc1: sdmmc@420c8000 { 754 compatible = "st,stm32-sdmmc"; 755 reg = <0x420c8000 0x400>; 756 clocks = <&rcc STM32_CLOCK(AHB2, 27U)>, 757 <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>; 758 resets = <&rctl STM32_RESET(AHB2L, 27U)>; 759 interrupts = <78 0>; 760 status = "disabled"; 761 }; 762 763 sdmmc2: sdmmc@420c8c00 { 764 compatible = "st,stm32-sdmmc"; 765 reg = <0x420c8c00 0x400>; 766 clocks = <&rcc STM32_CLOCK(AHB2, 28U)>, 767 <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>; 768 resets = <&rctl STM32_RESET(AHB2L, 28U)>; 769 interrupts = <79 0>; 770 status = "disabled"; 771 }; 772 773 dac1: dac@46021800 { 774 compatible = "st,stm32-dac"; 775 reg = <0x46021800 0x400>; 776 clocks = <&rcc STM32_CLOCK(AHB3, 6U)>; 777 status = "disabled"; 778 #io-channel-cells = <1>; 779 }; 780 781 adc1: adc@42028000 { 782 compatible = "st,stm32-adc"; 783 reg = <0x42028000 0x400>; 784 clocks = <&rcc STM32_CLOCK(AHB2, 10U)>, 785 <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; 786 interrupts = <37 0>; 787 status = "disabled"; 788 #io-channel-cells = <1>; 789 resolutions = <STM32_ADC_RES(14, 0x00) 790 STM32_ADC_RES(12, 0x01) 791 STM32_ADC_RES(10, 0x02) 792 STM32_ADC_RES(8, 0x03)>; 793 sampling-times = <5 6 12 20 36 68 391 814>; 794 st,adc-clock-source = "ASYNC"; 795 st,adc-sequencer = "FULLY_CONFIGURABLE"; 796 st,adc-oversampler = "OVERSAMPLER_EXTENDED"; 797 }; 798 799 adc4: adc@46021000 { 800 compatible = "st,stm32-adc"; 801 reg = <0x46021000 0x400>; 802 clocks = <&rcc STM32_CLOCK(AHB3, 5U)>, 803 <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; 804 interrupts = <113 0>; 805 status = "disabled"; 806 #io-channel-cells = <1>; 807 resolutions = <STM32_ADC_RES(12, 0x00) 808 STM32_ADC_RES(10, 0x01) 809 STM32_ADC_RES(8, 0x02) 810 STM32_ADC_RES(6, 0x03)>; 811 sampling-times = <2 4 8 13 20 40 80 815>; 812 num-sampling-time-common-channels = <2>; 813 st,adc-clock-source = "ASYNC"; 814 st,adc-sequencer = "NOT_FULLY_CONFIGURABLE"; 815 st,adc-oversampler = "OVERSAMPLER_MINIMAL"; 816 }; 817 818 fdcan1: can@4000a400 { 819 compatible = "st,stm32-fdcan"; 820 reg = <0x4000a400 0x400>, <0x4000ac00 0x350>; 821 reg-names = "m_can", "message_ram"; 822 interrupts = <39 0>, <40 0>; 823 interrupt-names = "int0", "int1"; 824 clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>; 825 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; 826 status = "disabled"; 827 }; 828 829 ucpd1: ucpd@4000dc00 { 830 compatible = "st,stm32-ucpd"; 831 reg = <0x4000dc00 0x400>; 832 clocks = <&rcc STM32_CLOCK(APB1, 23U)>; 833 interrupts = <106 0>; 834 status = "disabled"; 835 }; 836 837 gpdma1: dma@40020000 { 838 compatible = "st,stm32u5-dma"; 839 #dma-cells = <3>; 840 reg = <0x40020000 0x400>; 841 interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0 842 80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>; 843 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; 844 dma-channels = <16>; 845 dma-requests = <114>; 846 dma-offset = <0>; 847 status = "disabled"; 848 }; 849 850 fmc: memory-controller@420d0400 { 851 compatible = "st,stm32-fmc"; 852 reg = <0x420d0400 0x400>; 853 clocks = <&rcc STM32_CLOCK(AHB2_2, 0U)>; 854 status = "disabled"; 855 856 sram { 857 compatible = "st,stm32-fmc-nor-psram"; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 status = "disabled"; 861 }; 862 }; 863 864 pwr: power@46020800 { 865 compatible = "st,stm32-pwr"; 866 reg = <0x46020800 0x400>; /* PWR register bank */ 867 status = "disabled"; 868 869 wkup-pins-nb = <8>; /* 8 system wake-up pins */ 870 wkup-pin-srcs = <3>; /* 3 gpio sources associated with each wkup pin */ 871 wkup-pins-pol; 872 wkup-pins-pupd; 873 874 #address-cells = <1>; 875 #size-cells = <0>; 876 877 wkup-pin@1 { 878 reg = <0x1>; 879 wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>, 880 <&gpiob 2 STM32_PWR_WKUP_PIN_SRC_1>, 881 <&gpioe 4 STM32_PWR_WKUP_PIN_SRC_2>; 882 }; 883 884 wkup-pin@2 { 885 reg = <0x2>; 886 wkup-gpios = <&gpioa 4 STM32_PWR_WKUP_PIN_SRC_0>, 887 <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_1>, 888 <&gpioe 5 STM32_PWR_WKUP_PIN_SRC_2>; 889 }; 890 891 wkup-pin@3 { 892 reg = <0x3>; 893 wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_SRC_0>, 894 <&gpioa 1 STM32_PWR_WKUP_PIN_SRC_1>, 895 <&gpiob 6 STM32_PWR_WKUP_PIN_SRC_2>; 896 }; 897 898 wkup-pin@4 { 899 reg = <0x4>; 900 wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>, 901 <&gpiob 1 STM32_PWR_WKUP_PIN_SRC_1>, 902 <&gpiob 7 STM32_PWR_WKUP_PIN_SRC_2>; 903 }; 904 905 wkup-pin@5 { 906 reg = <0x5>; 907 wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_SRC_0>, 908 <&gpioa 3 STM32_PWR_WKUP_PIN_SRC_1>, 909 <&gpiob 8 STM32_PWR_WKUP_PIN_SRC_2>; 910 }; 911 912 wkup-pin@6 { 913 reg = <0x6>; 914 wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_PIN_SRC_0>, 915 <&gpioa 5 STM32_PWR_WKUP_PIN_SRC_1>, 916 <&gpioe 7 STM32_PWR_WKUP_PIN_SRC_2>; 917 }; 918 919 wkup-pin@7 { 920 reg = <0x7>; 921 wkup-gpios = <&gpiob 15 STM32_PWR_WKUP_PIN_SRC_0>, 922 <&gpioa 6 STM32_PWR_WKUP_PIN_SRC_1>, 923 <&gpioe 8 STM32_PWR_WKUP_PIN_SRC_2>; 924 }; 925 926 wkup-pin@8 { 927 reg = <0x8>; 928 wkup-gpios = <&gpiof 2 STM32_PWR_WKUP_PIN_SRC_0>, 929 <&gpioa 7 STM32_PWR_WKUP_PIN_SRC_1>, 930 <&gpiob 10 STM32_PWR_WKUP_PIN_SRC_2>; 931 }; 932 }; 933 934 }; 935 936 swj_port: swj_port { 937 compatible = "swj-connector"; 938 pinctrl-0 = <&debug_jtms_swdio_pa13 &debug_jtck_swclk_pa14 939 &debug_jtdi_pa15 &debug_jtdo_swo_pb3 940 &debug_jtrst_pb4>; 941 pinctrl-1 = <&analog_pa13 &analog_pa14 &analog_pa15 942 &analog_pb3 &analog_pb4>; 943 pinctrl-names = "default", "sleep"; 944 }; 945 946 die_temp: dietemp { 947 compatible = "st,stm32-temp-cal"; 948 ts-cal1-addr = <0x0BFA0710>; 949 ts-cal2-addr = <0x0BFA0742>; 950 ts-cal1-temp = <30>; 951 ts-cal2-temp = <130>; 952 ts-cal-vrefanalog = <3000>; 953 ts-cal-resolution = <14>; 954 io-channels = <&adc1 19>; 955 status = "disabled"; 956 }; 957 958 vref1: vref_1 { 959 compatible = "st,stm32-vref"; 960 vrefint-cal-addr = <0x0BFA07A5>; 961 vrefint-cal-mv = <3000>; 962 io-channels = <&adc1 0>; 963 status = "disabled"; 964 }; 965 966 vref4: vref_4 { 967 compatible = "st,stm32-vref"; 968 vrefint-cal-addr = <0x0BFA07A5>; 969 vrefint-cal-mv = <3000>; 970 io-channels = <&adc4 0>; 971 status = "disabled"; 972 }; 973 974 vbat1: vbat_1 { 975 compatible = "st,stm32-vbat"; 976 ratio = <4>; 977 io-channels = <&adc1 18>; 978 status = "disabled"; 979 }; 980 981 vbat4: vbat_4 { 982 compatible = "st,stm32-vbat"; 983 ratio = <4>; 984 io-channels = <&adc4 14>; 985 status = "disabled"; 986 }; 987 988 smbus1: smbus1 { 989 compatible = "st,stm32-smbus"; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 i2c = <&i2c1>; 993 status = "disabled"; 994 }; 995 996 smbus2: smbus2 { 997 compatible = "st,stm32-smbus"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 i2c = <&i2c2>; 1001 status = "disabled"; 1002 }; 1003 1004 smbus3: smbus3 { 1005 compatible = "st,stm32-smbus"; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 i2c = <&i2c3>; 1009 status = "disabled"; 1010 }; 1011 1012 smbus4: smbus4 { 1013 compatible = "st,stm32-smbus"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 i2c = <&i2c4>; 1017 status = "disabled"; 1018 }; 1019}; 1020 1021&nvic { 1022 arm,num-irq-priority-bits = <4>; 1023}; 1024
