1# Intel CAVS SoC family configuration options
2#
3# Copyright (c) 2020-2024 Intel Corporation
4# SPDX-License-Identifier: Apache-2.0
5
6config SOC_FAMILY_INTEL_ADSP
7	select WINSTREAM
8	select ARCH_SUPPORTS_COREDUMP
9	select CPU_HAS_DCACHE
10	select ARCH_HAS_USERSPACE if XTENSA_MMU
11	imply XTENSA_MMU_DOUBLE_MAP
12	select CPU_CACHE_INCOHERENT
13
14if SOC_FAMILY_INTEL_ADSP
15
16rsource "*/Kconfig"
17
18config INTEL_ADSP_SIM
19	bool "Intel ADSP Simulator"
20	select SIMULATOR_XTENSA
21	help
22	  Running this SoC family in a simulator.
23
24if INTEL_ADSP_SIM
25
26config INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW
27	bool "No secondary core flow."
28	help
29	  Select if simulator doesn't use the normal secondary core flow
30	  to initialise secondary clocks.
31
32endif # INTEL_ADSP_SIM
33
34DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc
35DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc
36
37config INTEL_ADSP_IPC
38	bool "Driver for the host IPC interrupt delivery"
39	default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HOST_IPC)) if !SOF
40	default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_IDC)) if !SOF
41	help
42	  Driver for the host IPC interrupt delivery mechanism.
43	  Currently SOF has its own driver for this hardware.
44
45config MEMORY_WIN_0_SIZE
46	int "Size of memory window 0"
47	default 8192
48	help
49	  Size of memory window 0.
50
51	  This window is used for firmware status & outbox/uplink mbox.
52
53config MEMORY_WIN_1_SIZE
54	int "Size of memory window 1"
55	default 8192
56	help
57	  Size of memory window 1.
58
59	  This window is used for inbox/downlink mbox.
60
61config MEMORY_WIN_2_SIZE
62	int "Size of memory window 2"
63	default 8192
64	help
65	  Size of memory window 2.
66
67	  This window is used for debug.
68
69config MEMORY_WIN_3_SIZE
70	int "Size of memory window 3"
71	default 8192
72	help
73	  Size of memory window 3.
74
75	  This window is used for trace.
76
77config ADSP_CLOCK
78	bool
79	help
80	  Driver for the CAVS clocks. Allow type of clock (and
81	  thus frequency) to be chosen.
82
83config HP_SRAM_RESERVE
84	int "Bytes to reserve at start of HP-SRAM"
85	default 65536
86	help
87	  Bytes to reserve at the start of HP-SRAM.  Zephyr will not
88	  place any symbols here, though the host windows have
89	  addresses here.  The SOF application also makes direct use
90	  of this region, so be very careful changing this value.
91
92config ADSP_TRACE_SIMCALL
93	bool "Emit SIMCALL output in addition to window tracing"
94	help
95	  When true, the trace_out layer will also use a SIMCALL
96	  instruction to emit the passed data to the standard output
97	  of an enclosing simulator process.  All window contents will
98	  remain identical.
99
100config ADSP_NEED_POWER_ON_CACHE
101	bool
102	help
103	  Need to power cache SRAM banks on.
104
105config ADSP_INIT_HPSRAM
106	bool
107	default y
108	help
109	  Need to init HP SRAM.
110
111config ADSP_POWER_DOWN_HPSRAM
112	bool "Switch off HP SRAM during power down"
113	default n if ZTEST
114	default y
115	help
116	 Switch off HP SRAM during power down. Platform-configurable.
117
118config ADSP_DISABLE_L2CACHE_AT_BOOT
119	bool
120
121config ADSP_IMR_CONTEXT_SAVE
122	bool "Saves FW context into IMR before core is shut down"
123	default n
124	help
125	  When true, FW will store its entire context into IMR before
126	  entering D3 state. Later this context can be used to FW restore
127	  when Host power up DSP again.
128
129config XTENSA_CPU_IDLE_SPIN
130	bool "Use busy loop for k_cpu_idle"
131	help
132	  Use a spin loop instead of WAITI for the CPU idle state.
133
134config XTENSA_WAITI_BUG
135	bool "Workaround sequence for WAITI bug on LX6"
136	help
137	  SOF traditionally contains this workaround on its ADSP
138	  platforms which prefixes a WAITI entry with 128 NOP
139	  instructions followed by an ISYNC and EXTW.
140
141config ADSP_IDLE_CLOCK_GATING
142	bool "DSP clock gating in Idle"
143	help
144	  When true, FW will run with enabled clock gating. This options change
145	  HW configuration of a DSP. Evry time core goes to the WAITI state
146	  (wait for interrupt) during idle, the clock can be gated (however, this
147	  does not mean that this will happen).
148
149endif # SOC_FAMILY_INTEL_ADSP
150