1.. zephyr:board:: osd32mp1_brk
2
3Overview
4********
5
6The OSD32MP1-BRK development board by Octavo Systems integrates the OSD32MP15x
7System-in-Package (SiP), which contains a multicore STM32MP157F microprocessor.
8Zephyr OS is ported to run on the Cortex®-M4 core of the STM32MP157F.
9
10- Common features:
11
12  - OSD32MP15x SiP:
13
14    - STM32MP15x microprocessor:
15      - Dual-core Arm® Cortex®-A7 up to 800 MHz, 32 bits
16      - Cortex®-M4 up to 209 MHz, 32 bits
17      - Embedded SRAM (448 Kbytes) for Cortex®-M4.
18
19    - 512MB DDR3 memory
20    - STPMIC1A Power Management
21    - Integrated 4kB EEPROM
22    - MEMS oscillator
23    - Over 100 passive components
24
25  - Small form factor:
26    - Dimensions: 75 mm x 46 mm (3 in x 1.8 in)
27    - Breadboard-compatible with access to 106 I/Os via two 2x30 100-mil headers
28
29  - Built-in features:
30    - μUSB
31    - ST-Link header
32    - UART
33    - μSD card slot
34    - 32 kHz crystal
35    - User LEDs and reset button
36    - 4 Layer Design
37    - No Back Side Components
38
39For a detailed list of features, visit the `OSD32MP1-BRK product page`_.
40
41Hardware
42********
43
44The OSD32MP15x SiP in integration with the STM32MP17 SoC provides the following hardware capabilities:
45
46- Core:
47
48  - 32-bit dual-core Arm® Cortex®-A7
49
50    - L1 32-Kbyte I / 32-Kbyte D for each core
51    - 256-Kbyte unified level 2 cache
52    - Arm® NEON™ and Arm® TrustZone®
53
54  - 32-bit Arm® Cortex®-M4 with FPU/MPU
55
56    - Up to 209 MHz (Up to 703 CoreMark®)
57
58- Memories:
59
60  - 512 MB DDR3L memory (on SiP)
61  - 708 Kbytes of internal SRAM:
62    - 256 KB AXI SYSRAM
63    - 384 KB AHB SRAM
64    - 64 KB AHB SRAM in backup domain
65  - Dual mode Quad-SPI memory interface
66  - Flexible external memory controller with up to 16-bit data bus
67  - Integrated 4 KB EEPROM (on SiP)
68
69- Security/safety:
70
71  - Secure boot, TrustZone® peripherals with Cortex®-M4 resource isolation
72
73- Clock management:
74
75  - Internal oscillators:
76    - 64 MHz HSI oscillator
77    - 4 MHz CSI oscillator
78    - 32 kHz LSI oscillator
79  - External oscillators:
80    - 8-48 MHz HSE oscillator
81    - 32.768 kHz LSE oscillator
82  - 6 × PLLs with fractional mode
83  - MEMS oscillator (on SiP)
84
85- General-purpose input/outputs:
86
87  - Up to 176 I/O ports with interrupt capability
88  - 106 I/Os routed to expansion headers (on board)
89
90- Interconnect matrix
91
92- 3 DMA controllers
93
94- Communication peripherals:
95
96  - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus)
97  - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)
98  - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy)
99  - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx)
100  - SPDIF Rx with 4 inputs
101  - HDMI-CEC interface
102  - MDIO Slave interface
103  - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO)
104  - 2 × CAN controllers supporting CAN FD protocol, TTCAN capability
105  - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously
106  - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
107  - 8- to 14-bit camera interface up to 140 Mbyte/s
108  - 6 analog peripherals
109  - 2 × ADCs with 16-bit max. resolution
110  - 1 × temperature sensor
111  - 2 × 12-bit D/A converters (1 MHz)
112  - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6
113    filters
114  - Internal or external ADC/DAC reference VREF+
115
116- Graphics:
117
118  - 3D GPU: Vivante® - OpenGL® ES 2.0
119  - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps
120  - MIPI® DSI 2 data lanes up to 1 GHz each
121
122- Timers:
123
124  - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature
125    (incremental) encoder input
126  - 2 × 16-bit advanced motor control timers
127  - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM)
128  - 5 × 16-bit low-power timers
129  - RTC with sub-second accuracy and hardware calendar
130  - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
131  - 1 × SysTick Cortex®-M4 timer
132
133- Hardware acceleration:
134
135  - AES 128, 192, 256, TDES
136  - HASH (MD5, SHA-1, SHA224, SHA256), HMAC
137  - 2 × true random number generator (3 oscillators each)
138  - 2 × CRC calculation unit
139
140- Debug mode:
141
142  - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces
143  - 8-Kbyte embedded trace buffer
144  - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user
145
146More information about the hardware can be found here:
147
148- `STM32MP157F on www.st.com`_
149- `OSD32MP15x SiP documentation`_
150
151Supported Features
152==================
153
154.. zephyr:board-supported-hw::
155
156Connections and IOs
157===================
158
159OSD32MP1-BRK Board schematic is available here:
160`OSD32MP1-BRK schematics`_.
161
162OSD32MP1-BRK Board pin mapping is available here:
163`OSD32MP1-BRK default pin mapping`_.
164
165Default Zephyr Peripheral Mapping:
166----------------------------------
167
168- UART7 TX/RX: PA15/PB3 (default console)
169- I2C5 SCL/SDA: PA11/PA12
170- SPI4 SCK/MISO/MOSI: PE12/PE13/PE14
171
172System Clock
173------------
174
175The Cortex®-M4 Core is configured to run at a 209 MHz clock speed.
176This value must match the configured mlhclk_ck frequency.
177
178Serial Port
179-----------
180
181The Zephyr console output is assigned by default to the RAM console to be dumped
182by the Linux Remoteproc Framework on Cortex®-A7 core. To enable the USART2 console, modify
183the board's devicetree and the osd32mp1_brk_defconfig board file (or prj.conf project files)
184Default USART settings are 115200 8N1.
185
186Programming and Debugging
187*************************
188
189The STM32MP157F doesn't have QSPI flash for Cortex®-M4 and it needs to be
190started by the Cortex®-A7 core. The Cortex®-A7 core is responsible for loading the
191Cortex®-M4 binary application into the RAM, and getting Cortex®-M4 out of reset.
192Cortex®-A7 can perform these steps at bootloader level or after the Linux
193system has booted.
194
195Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at
196the 0x00000000 (RETRAM) address, and the vector table should be loaded at this address.
197The following table provides memory mappings for Cortex®-A7 and Cortex®-M4:
198
199+------------+-----------------------+------------------------+----------------+
200| Region     | Cortex®-A7            | Cortex®-M4             | Size           |
201+============+=======================+========================+================+
202| RETRAM     | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF  | 64KB           |
203+------------+-----------------------+------------------------+----------------+
204| MCUSRAM    | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF  | 384KB          |
205+------------+-----------------------+------------------------+----------------+
206| DDR        | 0xC0000000-0x20000000 |                        | 512MB          |
207+------------+-----------------------+------------------------+----------------+
208
209Refer to following instructions to boot Zephyr on the Cortex®-M4 core:
210
2111. Download and install the Octavo OpenSTLinux distribution:
212   `OSD32MP1 OpenSTLinux`_.
213
214   (You can find more details about this process here: `OSD32MP1-BRK Getting Started`_)
215
2162. Build the Zephyr application:
217
218   .. zephyr-app-commands::
219      :zephyr-app: samples/hello_world
220      :board: osd32mp1_brk
221      :goals: build
222
2233. Transfer the built firmware to the board via USB RNDIS:
224
225   .. code-block:: console
226
227      scp build/zephyr/zephyr.elf root@192.168.7.1:/lib/firmware
228
2294. Boot Zephyr on the Cortex®-M4 core:
230
231   .. code-block:: console
232
233      ssh root@192.168.7.1
234      echo stop > /sys/class/remoteproc/remoteproc0/state
235      echo -n zephyr.elf > /sys/class/remoteproc/remoteproc0/firmware
236      echo start > /sys/class/remoteproc/remoteproc0/state
237      cat /sys/kernel/debug/remoteproc/remoteproc0/trace0
238
239   The console output should display:
240
241   .. code-block::
242
243      *** Booting Zephyr OS build v4.0.0 ***
244      Hello World! osd32mp1_brk/osd32mp15x
245
246
247Refer to `OSD32MP1-BRK Getting Started`_ and `stm32mp157 boot Cortex-M4 firmware`_ wiki page for more
248detailed instructions.
249
250Debugging
251=========
252
253You can debug an application using OpenOCD and GDB. The solution proposed below
254is based on attaching to preloaded firmware, which is available only for a Linux
255environment. The firmware must first be loaded by the Cortex®-A7. The developer
256then attaches the debugger to the running Zephyr using OpenOCD.
257
258The principle is to attach to the firmware already loaded by Linux.
259
260- Build the sample:
261
262  .. zephyr-app-commands::
263     :zephyr-app: samples/hello_world
264     :board: osd32mp1_brk
265     :goals: build
266
267- Copy the firmware on the target filesystem, load it and start it (`stm32mp157 boot Cortex-M4 firmware`_).
268- Attach to the target:
269
270  .. code-block:: console
271
272    west attach
273
274.. _OSD32MP1-BRK product page:
275   https://octavosystems.com/octavo_products/osd32mp1-brk/
276
277.. _OSD32MP1-BRK documentation:
278   https://octavosystems.com/docs/osd32mp15x-datasheet/
279
280.. _STM32MP157F on www.st.com:
281   https://www.st.com/en/microcontrollers-microprocessors/stm32mp157f.html
282
283.. _OSD32MP15x SiP documentation:
284   https://octavosystems.com/docs/osd32mp15x-datasheet/
285
286.. _OSD32MP1 OpenSTLinux:
287   https://octavosystems.com/files/osd32mp1-brk-openstlinux-v3-0/
288
289.. _OSD32MP1-BRK Getting Started:
290    https://octavosystems.com/app_notes/osd32mp1-brk-getting-started/
291
292.. _stm32mp157 boot Cortex-M4 firmware:
293   https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework
294
295.. _OSD32MP1-BRK schematics:
296   https://octavosystems.com/docs/osd32mp1-brk-schematics/
297
298.. _OSD32MP1-BRK default pin mapping:
299   https://octavosystems.com/octavosystems.com/wp-content/uploads/2020/05/Default-Pin-Mapping.pdf
300