1/*
2 * Copyright (c) 2021 Thomas Stranger
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <seeed_studio/lora-e5.dtsi>
9#include <zephyr/dt-bindings/input/input-event-codes.h>
10
11/ {
12	model = "Seeed Studio LoRa-E5 Dev Board";
13	compatible = "seeed,lora-e5-dev-board";
14
15	chosen {
16		zephyr,console = &usart1;
17		zephyr,shell-uart = &usart1;
18		zephyr,sram = &sram0;
19		zephyr,flash = &flash0;
20		zephyr,code-partition = &slot0_partition;
21	};
22
23	leds {
24		compatible = "gpio-leds";
25		red_led_1: led_0 {
26			gpios = <&gpiob 5 GPIO_ACTIVE_LOW>;
27			label = "User LED1";
28			/* the led can be disconnected, using J16 (D5) */
29		};
30	};
31
32	gpio_keys {
33		compatible = "gpio-keys";
34		boot_button: button_0 {
35			label = "SW1";
36			gpios = <&gpiob 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
37			zephyr,code = <INPUT_KEY_0>;
38		};
39
40		user_button: button_1 {
41			label = "SW2";
42			gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
43			/* user_button can be disconnected, using J14 (D0) */
44			zephyr,code = <INPUT_KEY_1>;
45		};
46	};
47
48	aliases {
49		led0 = &red_led_1;
50		sw0 = &boot_button;
51		sw1 = &user_button;
52		lora0 = &lora;
53		watchdog0 = &iwdg;
54	};
55
56	pwr_3v3: pwr-3v3-ctrl {
57		/*
58		 * PWR rail for SPI-flash, Temp-Sensor, RS-485 Transceiver,
59		 * and for external devices(Grove, header).
60		 * Requires closed J15 (D9)
61		 */
62		compatible = "regulator-fixed";
63		regulator-name = "pwr-3v3-ctrl";
64		enable-gpios = <&gpioa 9 GPIO_ACTIVE_HIGH>;
65		regulator-boot-on;
66		status = "okay";
67	};
68
69	pwr_5v: pwr-5v-ctrl {
70		/*
71		 * Available for external devices on header J2
72		 * Requires closed J6 (D10)
73		 */
74		compatible = "regulator-fixed";
75		regulator-name = "pwr-5v-ctrl";
76		enable-gpios = <&gpiob 10 GPIO_ACTIVE_HIGH>;
77		regulator-boot-on;
78		status = "okay";
79	};
80};
81
82stm32_lp_tick_source: &lptim1 {
83	status = "okay";
84	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
85		 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
86};
87
88&clk_lsi {
89	status = "okay";
90};
91
92&clk_msi {
93	status = "okay";
94	msi-range = <11>;
95};
96
97&rcc {
98	clocks = <&clk_msi>;
99	clock-frequency = <DT_FREQ_M(48)>;
100	cpu1-prescaler = <1>;
101	ahb3-prescaler = <1>;
102	apb1-prescaler = <1>;
103	apb2-prescaler = <1>;
104};
105
106&lpuart1 {
107	pinctrl-0 = <&lpuart1_tx_pc1 &lpuart1_rx_pc0>;
108	pinctrl-names = "default";
109	current-speed = <115200>;
110	status = "okay";
111};
112
113&usart1 {
114	pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
115	pinctrl-names = "default";
116	current-speed = <115200>;
117	status = "okay";
118};
119
120&usart2 {
121	pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
122	pinctrl-names = "default";
123	current-speed = <115200>;
124	status = "okay";
125	/* PB4 can select RS-485 TX, when J17 (A4) is closed */
126};
127
128&i2c2 {
129	pinctrl-0 = <&i2c2_scl_pb15 &i2c2_sda_pa15>;
130	pinctrl-names = "default";
131	status = "okay";
132	clock-frequency = <I2C_BITRATE_FAST>;
133
134	/* LM75ADP temperature sensor on addr 0x48 */
135};
136
137/* Attention!: the spi-sck pin is in conflict with the boot_button on pb13 */
138&spi2 {
139	pinctrl-0 = <&spi2_nss_pb9 &spi2_sck_pb13
140		     &spi2_miso_pb14 &spi2_mosi_pa10>;
141	pinctrl-names = "default";
142	status = "okay";
143
144	/* unpopulated footprint for spi flash */
145};
146
147&rtc {
148	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
149		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
150	status = "okay";
151};
152
153&iwdg {
154	status = "okay";
155};
156
157&adc1 {
158	pinctrl-0 = <&adc_in2_pb3>;
159	pinctrl-names = "default";
160	st,adc-clock-source = "SYNC";
161	st,adc-prescaler = <4>;
162	status = "okay";
163};
164
165&aes {
166	status = "okay";
167};
168
169/* connectors: */
170grove_serial: &usart1 {};
171grove_i2c: &i2c2 {};
172
173&flash0 {
174	partitions {
175		compatible = "fixed-partitions";
176		#address-cells = <1>;
177		#size-cells = <1>;
178
179		boot_partition: partition@0 {
180			label = "mcuboot";
181			reg = <0x00000000 DT_SIZE_K(32)>;
182			read-only;
183		};
184		slot0_partition: partition@8000 {
185			label = "image-0";
186			reg = <0x00008000 DT_SIZE_K(104)>;
187		};
188		slot1_partition: partition@22000 {
189			label = "image-1";
190			reg = <0x00022000 DT_SIZE_K(104)>;
191		};
192		/* 16KB (8x2kB pages) of storage at the end of the flash */
193		storage_partition: partition@3c000 {
194			label = "storage";
195			reg = <0x0003c000 DT_SIZE_K(16)>;
196		};
197	};
198};
199
200/*
201 * Other Pins:
202 * Not assigned:  None
203 * Debug:         PA13(swdio), PA14(swclk)
204 */
205