1/*
2 * Copyright (c) 2024 Pratik Farkase <pratik.farkase@wsisweden.com>
3 * Copyright (c) 2024 Sigma Connectivity WSI AB
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include "jh7110-clk.dtsi"
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <freq.h>
11
12/ {
13	#address-cells = <2>;
14	#size-cells = <2>;
15	compatible = "starfive,jh7110";
16	model = "starfive,jh7110";
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		S7_0: cpu@0 {
23			compatible = "sifive,s7", "riscv";
24			device_type = "cpu";
25			reg = <0>;
26			riscv,isa = "rv64imac_zicsr_zifencei";
27			status = "okay";
28			cpu0_intc: interrupt-controller {
29				compatible = "riscv,cpu-intc";
30				interrupt-controller;
31				#interrupt-cells = <1>;
32			};
33		};
34
35		U74_1: cpu@1 {
36			compatible = "sifive,u74", "riscv";
37			device_type = "cpu";
38			d-cache-block-size = <64>;
39			d-cache-sets = <64>;
40			d-cache-size = <32768>;
41			d-tlb-sets = <1>;
42			d-tlb-size = <40>;
43			i-cache-block-size = <64>;
44			i-cache-sets = <64>;
45			i-cache-size = <32768>;
46			i-tlb-sets = <1>;
47			i-tlb-size = <40>;
48			mmu-type = "riscv,sv39";
49			next-level-cache = <&ccache>;
50			reg = <0x1>;
51			riscv,isa = "rv64imafdcg";
52			tlb-spilt;
53			cpu1_intc: interrupt-controller {
54				compatible = "riscv,cpu-intc";
55				#interrupt-cells = <1>;
56				interrupt-controller;
57			};
58		};
59
60		U74_2: cpu@2 {
61			compatible = "sifive,u74", "riscv";
62			device_type = "cpu";
63			d-cache-block-size = <64>;
64			d-cache-sets = <64>;
65			d-cache-size = <32768>;
66			d-tlb-sets = <1>;
67			d-tlb-size = <40>;
68			i-cache-block-size = <64>;
69			i-cache-sets = <64>;
70			i-cache-size = <32768>;
71			i-tlb-sets = <1>;
72			i-tlb-size = <40>;
73			mmu-type = "riscv,sv39";
74			next-level-cache = <&ccache>;
75			reg = <0x2>;
76			riscv,isa = "rv64imafdcg";
77			tlb-split;
78			cpu2_intc: interrupt-controller {
79				compatible = "riscv,cpu-intc";
80				#interrupt-cells = <1>;
81				interrupt-controller;
82			};
83		};
84
85		U74_3: cpu@3 {
86			compatible = "sifive,u74", "riscv";
87			device_type = "cpu";
88			d-cache-block-size = <64>;
89			d-cache-sets = <64>;
90			d-cache-size = <32768>;
91			d-tlb-sets = <1>;
92			d-tlb-size = <40>;
93			i-cache-block-size = <64>;
94			i-cache-sets = <64>;
95			i-cache-size = <32768>;
96			i-tlb-sets = <1>;
97			i-tlb-size = <40>;
98			mmu-type = "riscv,sv39";
99			next-level-cache = <&ccache>;
100			reg = <0x3>;
101			riscv,isa = "rv64imafdcg";
102			tlb-split;
103			cpu3_intc: interrupt-controller {
104				compatible = "riscv,cpu-intc";
105				#interrupt-cells = <1>;
106				interrupt-controller;
107			};
108		};
109
110		U74_4: cpu@4 {
111			compatible = "sifive,u74", "riscv";
112			device_type = "cpu";
113			d-cache-block-size = <64>;
114			d-cache-sets = <64>;
115			d-cache-size = <32768>;
116			d-tlb-sets = <1>;
117			d-tlb-size = <40>;
118			i-cache-block-size = <64>;
119			i-cache-sets = <64>;
120			i-cache-size = <32768>;
121			i-tlb-sets = <1>;
122			i-tlb-size = <40>;
123			mmu-type = "riscv,sv39";
124			next-level-cache = <&ccache>;
125			reg = <0x4>;
126			riscv,isa = "rv64imafdcg";
127			tlb-split;
128			cpu4_intc: interrupt-controller {
129				compatible = "riscv,cpu-intc";
130				#interrupt-cells = <1>;
131				interrupt-controller;
132			};
133		};
134	};
135
136	l2lim: memory@8000000 {
137		device_type = "memory";
138		reg = <0x0 0x8000000 0x0 0x200000>;
139	};
140
141	soc {
142		#address-cells = <2>;
143		#size-cells = <2>;
144		#clock-cells = <1>;
145		compatible = "starfive,jh7110", "simple-bus";
146		ranges;
147
148		clint: timer@2000000 {
149			compatible = "starfive,jh7110-clint", "sifive,clint0";
150			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
151						&cpu1_intc 3 &cpu1_intc 7
152						&cpu2_intc 3 &cpu2_intc 7
153						&cpu3_intc 3 &cpu3_intc 7
154						&cpu4_intc 3 &cpu4_intc 7>;
155			reg = <0x0 0x2000000 0x0 0x10000>;
156		};
157
158		ccache: cache-controller@2010000 {
159			cache-block-size = <64>;
160			cache-level = <2>;
161			cache-sets = <2048>;
162			cache-size = <2097152>;
163			cache-unified;
164			compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
165			interrupt-parent = <&plic>;
166			interrupts = <1>, <3>, <4>, <2>;
167			reg = <0x0 0x2010000 0x0 0x4000>;
168		};
169
170		plic: interrupt-controller@c000000 {
171			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
172			#address-cells = <0>;
173			#interrupt-cells = <2>;
174			interrupt-controller;
175			interrupts-extended = <&cpu0_intc 11>,
176						<&cpu1_intc 11>, <&cpu1_intc 9>,
177						<&cpu2_intc 11>, <&cpu2_intc 9>,
178						<&cpu3_intc 11>, <&cpu3_intc 9>,
179						<&cpu4_intc 11>, <&cpu4_intc 9>;
180			reg = <0x0 0x0c000000 0x0 0x04000000>;
181			riscv,max-priority = <7>;
182			riscv,ndev = <52>;
183		};
184
185		uart0: serial@10000000 {
186			compatible = "ns16550", "snps,dw-apb-uart";
187			clocks = <&uartclk>, <&apb2clk>;
188			clock-names = "baudclk", "apb_pclk";
189			clock-frequency = <100000000>;
190			current-speed = <115200>;
191			interrupt-parent = <&plic>;
192			interrupts = <32 1>;
193			reg = <0x0 0x10000000 0x0 0x10000>;
194			reg-shift = <2>;
195			status = "disabled";
196		};
197
198		uart1: serial@10010000 {
199			compatible = "ns16550", "snps,dw-apb-uart";
200			clocks = <&uartclk>, <&apb2clk>;
201			clock-names = "baudclk", "apb_pclk";
202			clock-frequency = <100000000>;
203			current-speed = <115200>;
204			interrupt-parent = <&plic>;
205			interrupts = <33 1>;
206			reg = <0x0 0x10010000 0x0 0x10000>;
207			reg-shift = <2>;
208			status = "disabled";
209		};
210	};
211};
212