Searched refs:shim_base (Results 1 – 5 of 5) sorted by relevance
143 sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | in dai_dmic_claim_ownership()144 FIELD_PREP(DMICLCTL_OSEL, 0x3), dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_claim_ownership()150 sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & in dai_dmic_release_ownership()151 ~DMICLCTL_OSEL, dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_release_ownership()166 return dmic->shim_base; in dai_dmic_base()294 sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMICLCTL_DCGD), in dai_dmic_dis_clk_gating()295 dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_dis_clk_gating()306 sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMICLCTL_DCGD), in dai_dmic_en_clk_gating()307 dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_en_clk_gating()318 uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index; in dai_dmic_program_channel_map()[all …]
175 uint32_t shim_base; member
291 val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_clock_select_set()294 sys_write32(val, dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_clock_select_set()310 val = sys_read32(dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_clock_select_get()329 if (clock_source && !(sys_read32(dmic->shim_base + DMICLCAP_OFFSET) & DMICLCAP_MLCS)) { in dai_dmic_set_clock()
136 uint32_t shim_base; member
31 #define dai_shim_base(dai) dai->ssp_plat_data->shim_base69 .shim_base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(shim), 0), \
