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Searched refs:s32i (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/arch/xtensa/core/
Duserspace.S62 s32i a1, a0, ___xtensa_irq_bsa_t_scratch_OFFSET
63 s32i a2, a0, ___xtensa_irq_bsa_t_a2_OFFSET
64 s32i a3, a0, ___xtensa_irq_bsa_t_a3_OFFSET
66 s32i a2, a0, ___xtensa_irq_bsa_t_a0_OFFSET
70 s32i a2, a0, ___xtensa_irq_bsa_t_ps_OFFSET
72 s32i a2, a0, ___xtensa_irq_bsa_t_pc_OFFSET
120 s32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET
153 s32i a3, a0, 0
179 s32i a3, a1, 0
205 s32i a6, a3, ___xtensa_irq_bsa_t_a2_OFFSET
[all …]
Dcrt1.S171 s32i a0, a8, 0 /* clear 4 bytes to make len multiple of 8 */
174 s32i a0, a8, 0 /* clear 8 bytes to make len multiple of 16 */
175 s32i a0, a8, 4
179 s32i a0, a8, 0 /* clear 16 bytes at a time... */
180 s32i a0, a8, 4
181 s32i a0, a8, 8
182 s32i a0, a8, 12
Dxtensa_asm2_util.S62 s32i a4, a1, 0
63 s32i a5, a1, 4
64 s32i a6, a1, 8
65 s32i a7, a1, 12
69 s32i a8, a1, 0
70 s32i a9, a1, 4
71 s32i a10, a1, 8
72 s32i a11, a1, 12
76 s32i a12, a1, 0
77 s32i a13, a1, 4
[all …]
Ddebug_helpers_asm.S31 s32i a7, a2, 0
35 s32i a7, a4, 0
39 s32i a6, a3, 0
/Zephyr-latest/arch/xtensa/include/
Dxtensa_asm2_s.h110 s32i a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
112 s32i a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
168 s32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET
171 s32i a0, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET
173 s32i a0, a1, ___xtensa_irq_bsa_t_lend_OFFSET
175 s32i a0, a1, ___xtensa_irq_bsa_t_lcount_OFFSET
178 s32i a0, a1, ___xtensa_irq_bsa_t_exccause_OFFSET
181 s32i a0, a1, ___xtensa_irq_bsa_t_scompare1_OFFSET
186 s32i a0, a1, ___xtensa_irq_bsa_t_threadptr_OFFSET
410 s32i a2, a1, ___xtensa_irq_bsa_t_scratch_OFFSET
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dasm_memory_management.h33 s32i \ay, \ax, 0
43 s32i \ay, \ax, 0
53 s32i \mask, \ax, 0
65 s32i \ay, \ax, 0
Dasm_ldo_management.h23 s32i \state, \ax, 0
83 s32i \ax, \ay, 0
103 s32i \ax, \ay, 0
Dpower_down_cavs.S132 s32i temp_reg1, host_base, IPC_DIPCIDD
136 s32i temp_reg1, host_base, IPC_DIPCIDR
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dpower_down.S137 s32i temp_reg1, p_ipc_regs, 0x180
139 s32i temp_reg0, p_ipc_regs, 0x10
/Zephyr-latest/arch/xtensa/core/startup/
Dreset_vector.S278 s32i a0, a2, 0 /* clear sync variable */
490 s32i a6, a3, 0
626 s32i a4, a5, 0