1 /* 2 * Copyright (c) 2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __DAI_PARAMS_INTEL_IPC4_H__ 8 #define __DAI_PARAMS_INTEL_IPC4_H__ 9 10 #include <stdint.h> 11 12 #define DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT 8 13 14 #define I2SIPCMC 8 15 #define I2SOPCMC 8 16 17 /**< Type of the gateway. */ 18 enum dai_intel_ipc4_connector_node_id_type { 19 /**< HD/A host output (-> DSP). */ 20 dai_intel_ipc4_hda_host_output_class = 0, 21 /**< HD/A host input (<- DSP). */ 22 dai_intel_ipc4_hda_host_input_class = 1, 23 /**< HD/A host input/output (rsvd for future use). */ 24 dai_intel_ipc4_hda_host_inout_class = 2, 25 26 /**< HD/A link output (DSP ->). */ 27 dai_intel_ipc4_hda_link_output_class = 8, 28 /**< HD/A link input (DSP <-). */ 29 dai_intel_ipc4_hda_link_input_class = 9, 30 /**< HD/A link input/output (rsvd for future use). */ 31 dai_intel_ipc4_hda_link_inout_class = 10, 32 33 /**< DMIC link input (DSP <-). */ 34 dai_intel_ipc4_dmic_link_input_class = 11, 35 36 /**< I2S link output (DSP ->). */ 37 dai_intel_ipc4_i2s_link_output_class = 12, 38 /**< I2S link input (DSP <-). */ 39 dai_intel_ipc4_i2s_link_input_class = 13, 40 41 /**< ALH link output, legacy for SNDW (DSP ->). */ 42 dai_intel_ipc4_alh_link_output_class = 16, 43 /**< ALH link input, legacy for SNDW (DSP <-). */ 44 dai_intel_ipc4_alh_link_input_class = 17, 45 46 /**< SNDW link output (DSP ->). */ 47 dai_intel_ipc4_alh_snd_wire_stream_link_output_class = 16, 48 /**< SNDW link input (DSP <-). */ 49 dai_intel_ipc4_alh_snd_wire_stream_link_input_class = 17, 50 51 /**< UAOL link output (DSP ->). */ 52 dai_intel_ipc4_alh_uaol_stream_link_output_class = 18, 53 /**< UAOL link input (DSP <-). */ 54 dai_intel_ipc4_alh_uaol_stream_link_input_class = 19, 55 56 /**< IPC output (DSP ->). */ 57 dai_intel_ipc4_ipc_output_class = 20, 58 /**< IPC input (DSP <-). */ 59 dai_intel_ipc4_ipc_input_class = 21, 60 61 /**< I2S Multi gtw output (DSP ->). */ 62 dai_intel_ipc4_i2s_multi_link_output_class = 22, 63 /**< I2S Multi gtw input (DSP <-). */ 64 dai_intel_ipc4_i2s_multi_link_input_class = 23, 65 /**< GPIO */ 66 dai_intel_ipc4_gpio_class = 24, 67 /**< SPI */ 68 dai_intel_ipc4_spi_output_class = 25, 69 dai_intel_ipc4_spi_input_class = 26, 70 dai_intel_ipc4_max_connector_node_id_type 71 }; 72 73 struct ssp_intel_aux_tlv { 74 uint32_t type; 75 uint32_t size; 76 uint32_t val[]; 77 } __packed; 78 79 struct ssp_intel_mn_ctl { 80 uint32_t div_m; 81 uint32_t div_n; 82 } __packed; 83 84 struct ssp_intel_clk_ctl { 85 uint32_t start; 86 uint32_t stop; 87 } __packed; 88 89 struct ssp_intel_tr_ctl { 90 uint32_t sampling_frequency; 91 uint32_t bit_depth; 92 uint32_t channel_map; 93 uint32_t channel_config; 94 uint32_t interleaving_style; 95 uint32_t format; 96 } __packed; 97 98 struct ssp_intel_run_ctl { 99 uint32_t enabled; 100 } __packed; 101 102 struct ssp_intel_node_ctl { 103 uint32_t node_id; 104 uint32_t sampling_rate; 105 } __packed; 106 107 struct ssp_intel_sync_ctl { 108 uint32_t sync_denominator; 109 uint32_t count; 110 } __packed; 111 112 struct ssp_intel_ext_ctl { 113 uint32_t ext_data; 114 } __packed; 115 116 struct ssp_intel_link_ctl { 117 uint32_t clock_source; 118 } __packed; 119 120 #define SSP_MN_DIVIDER_CONTROLS 0 121 #define SSP_DMA_CLK_CONTROLS 1 122 #define SSP_DMA_TRANSMISSION_START 2 123 #define SSP_DMA_TRANSMISSION_STOP 3 124 #define SSP_DMA_ALWAYS_RUNNING_MODE 4 125 #define SSP_DMA_SYNC_DATA 5 126 #define SSP_DMA_CLK_CONTROLS_EXT 6 127 #define SSP_LINK_CLK_SOURCE 7 128 129 /**< Base top-level structure of an address of a gateway. */ 130 /*! 131 * The virtual index value, presented on the top level as raw 8 bits, 132 * is expected to be encoded in a gateway specific way depending on 133 * the actual type of gateway. 134 */ 135 union dai_intel_ipc4_connector_node_id { 136 137 /**< Raw 32-bit value of node id. */ 138 uint32_t dw; 139 140 /**< Bit fields */ 141 struct { 142 /**< Index of the virtual DMA at the gateway. */ 143 uint32_t v_index : 8; 144 145 /**< Type of the gateway, one of ConnectorNodeId::Type values. */ 146 uint32_t dma_type : 5; 147 148 /**< Rsvd field. */ 149 uint32_t _rsvd : 19; 150 } f; /**<< Bits */ 151 } __packed; 152 153 /*! 154 * Attributes are usually provided along with the gateway configuration 155 * BLOB when the FW is requested to instantiate that gateway. 156 * 157 * There are flags which requests FW to allocate gateway related data 158 * (buffers and other items used while transferring data, like linked list) 159 * to be allocated from a special memory area, e.g low power memory. 160 */ 161 union dai_intel_ipc4_gateway_attributes { 162 163 /**< Raw value */ 164 uint32_t dw; 165 166 /**< Access to the fields */ 167 struct { 168 /**< Gateway data requested in low power memory. */ 169 uint32_t lp_buffer_alloc : 1; 170 171 /**< Gateway data requested in register file memory. */ 172 uint32_t alloc_from_reg_file : 1; 173 174 /**< Reserved field */ 175 uint32_t _rsvd : 30; 176 } bits; /**<< Bits */ 177 } __packed; 178 179 /**< Configuration for the IPC Gateway */ 180 struct dai_intel_ipc4_gateway_config_blob { 181 182 /**< Size of the gateway buffer, specified in bytes */ 183 uint32_t buffer_size; 184 185 /**< Flags */ 186 union flags { 187 struct bits { 188 /**< Activates high threshold notification */ 189 /*! 190 * Indicates whether notification should be sent to the host 191 * when the size of data in the buffer reaches the high threshold 192 * specified by threshold_high parameter. 193 */ 194 uint32_t notif_high : 1; 195 196 /**< Activates low threshold notification */ 197 /*! 198 * Indicates whether notification should be sent to the host 199 * when the size of data in the buffer reaches the low threshold 200 * specified by threshold_low parameter. 201 */ 202 uint32_t notif_low : 1; 203 204 /**< Reserved field */ 205 uint32_t rsvd : 30; 206 } f; /**<< Bits */ 207 /**< Raw value of flags */ 208 uint32_t flags_raw; 209 } u; /**<< Flags */ 210 211 /**< High threshold */ 212 /*! 213 * Specifies the high threshold (in bytes) for notifying the host 214 * about the buffered data level. 215 */ 216 uint32_t threshold_high; 217 218 /**< Low threshold */ 219 /*! 220 * Specifies the low threshold (in bytes) for notifying the host 221 * about the buffered data level. 222 */ 223 uint32_t threshold_low; 224 } __packed; 225 226 /* i2s Configuration BLOB building blocks */ 227 228 /* i2s registers for i2s Configuration */ 229 struct dai_intel_ipc4_ssp_config { 230 uint32_t ssc0; 231 uint32_t ssc1; 232 uint32_t sscto; 233 uint32_t sspsp; 234 uint32_t sstsa; 235 uint32_t ssrsa; 236 uint32_t ssc2; 237 uint32_t sspsp2; 238 uint32_t ssc3; 239 uint32_t ssioc; 240 } __packed; 241 242 struct dai_intel_ipc4_ssp_config_ver_3_0 { 243 uint32_t ssc0; 244 uint32_t ssc1; 245 uint32_t sscto; 246 uint32_t sspsp; 247 uint32_t ssc2; 248 uint32_t sspsp2; 249 uint32_t ssc3; 250 uint32_t ssioc; 251 /* Specifies which time slots the DMA FIFO will receive from the SSP Interface*/ 252 uint64_t ssmidytsa[I2SIPCMC]; 253 /* Specifies which time slots the DMA FIFO will transmit to the SSP Interface */ 254 uint64_t ssmodytsa[I2SOPCMC]; 255 } __packed; 256 257 struct dai_intel_ipc4_ssp_mclk_config { 258 /* master clock divider control register */ 259 uint32_t mdivc; 260 261 /* master clock divider ratio register */ 262 uint32_t mdivr; 263 } __packed; 264 265 struct dai_intel_ipc4_ssp_mclk_config_2 { 266 uint32_t mdivctlr; 267 uint32_t mdivrcnt; 268 uint32_t mdivr[]; 269 } __packed; 270 271 struct dai_intel_ipc4_ssp_driver_config { 272 #ifdef CONFIG_SOC_INTEL_ACE30 273 struct dai_intel_ipc4_ssp_config_ver_3_0 i2s_config; 274 #else 275 struct dai_intel_ipc4_ssp_config i2s_config; 276 #endif 277 struct dai_intel_ipc4_ssp_mclk_config mclk_config; 278 } __packed; 279 280 struct dai_intel_ipc4_ssp_start_control { 281 /* delay in msec between enabling interface (moment when 282 * Copier instance is being attached to the interface) and actual 283 * interface start. Value of 0 means no delay. 284 */ 285 uint32_t clock_warm_up : 16; 286 287 /* specifies if parameters target MCLK (1) or SCLK (0) */ 288 uint32_t mclk : 1; 289 290 /* value of 1 means that clock should be started immediately 291 * even if no Copier instance is currently attached to the interface. 292 */ 293 uint32_t warm_up_ovr : 1; 294 uint32_t rsvd0 : 14; 295 } __packed; 296 297 struct dai_intel_ipc4_ssp_stop_control { 298 /* delay in msec between stopping the interface 299 * (moment when Copier instance is being detached from the interface) 300 * and interface clock stop. Value of 0 means no delay. 301 */ 302 uint32_t clock_stop_delay : 16; 303 304 /* value of 1 means that clock should be kept running (infinite 305 * stop delay) after Copier instance detaches from the interface. 306 */ 307 uint32_t keep_running : 1; 308 309 /* value of 1 means that clock should be stopped immediately */ 310 uint32_t clock_stop_ovr : 1; 311 uint32_t rsvd1 : 14; 312 } __packed; 313 314 union dai_intel_ipc4_ssp_dma_control { 315 struct dai_intel_ipc4_ssp_control { 316 struct dai_intel_ipc4_ssp_start_control start_control; 317 struct dai_intel_ipc4_ssp_stop_control stop_control; 318 } control_data; 319 320 struct dai_intel_ipc4_mn_div_config { 321 uint32_t mval; 322 uint32_t nval; 323 } mndiv_control_data; 324 } __packed; 325 326 struct dai_intel_ipc4_ssp_configuration_blob { 327 union dai_intel_ipc4_gateway_attributes gw_attr; 328 329 /* TDM time slot mappings */ 330 uint32_t tdm_ts_group[DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT]; 331 332 /* i2s port configuration */ 333 struct dai_intel_ipc4_ssp_driver_config i2s_driver_config; 334 335 /* optional configuration parameters */ 336 FLEXIBLE_ARRAY_DECLARE(union dai_intel_ipc4_ssp_dma_control, i2s_dma_control); 337 } __packed; 338 339 #define SSP_BLOB_VER_1_5 0xee000105 340 341 struct dai_intel_ipc4_ssp_configuration_blob_ver_1_5 { 342 union dai_intel_ipc4_gateway_attributes gw_attr; 343 344 uint32_t version; 345 uint32_t size; 346 347 /* TDM time slot mappings */ 348 uint32_t tdm_ts_group[DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT]; 349 350 /* i2s port configuration */ 351 struct dai_intel_ipc4_ssp_config i2s_ssp_config; 352 /* clock configuration parameters */ 353 struct dai_intel_ipc4_ssp_mclk_config_2 i2s_mclk_control; 354 } __packed; 355 356 #define SSP_BLOB_VER_3_0 0xee000300 357 358 struct dai_intel_ipc4_ssp_configuration_blob_ver_3_0 { 359 union dai_intel_ipc4_gateway_attributes gw_attr; 360 361 uint32_t version; 362 uint32_t size; 363 364 /* TDM time slot mappings */ 365 uint32_t tdm_ts_group[DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT]; 366 367 /* i2s port configuration */ 368 struct dai_intel_ipc4_ssp_config_ver_3_0 i2s_ssp_config; 369 /* clock configuration parameters */ 370 struct dai_intel_ipc4_ssp_mclk_config_2 i2s_mclk_control; 371 } __packed; 372 373 #endif 374
