1.. zephyr:board:: ls1046ardb
2
3Overview
4********
5
6The LS1046A reference design board (RDB) is a high-performance computing,
7evaluation, and development platform that supports the Layerscape LS1046A
8architecture processor. The LS1046ARDB board supports the Layerscape LS1046A
9processor and is optimized to support the DDR4 memory and a full complement
10of high-speed SerDes ports.
11
12The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72
13cores with packet processing acceleration and high-speed peripherals. The
14impressive performance of more than 32,000 CoreMarks, paired with 10 Gb
15Ethernet, PCIe Gen. 3, SATA 3.0, USB 3.0 and QSPI interfaces provides an
16excellent combination for a range of enterprise and service provider
17networking, storage, security and industrial applications.
18
19Hardware
20********
21
22LS1046A RDB boards supports the following features:
23
24
25- Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed
26- Supports 8 GB DDR4 SDRAM memory
27- SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi
28  memory device
29- One 512 MB SLC NAND flash with ECC support (1.8 V)
30- CPLD connection: 8-bit registers in CPLD to configure mux/demux selections
31- Support two 64 MB onboard QSPI NOR flash memories
32- USB:
33  - Two USB 3.0 controllers with integrated PHYs.
34  - One USB1 3.0 port is connected to a Type A host connector.
35  - One USB1 3.0 port is configured as On-The-Go (OTG) with a Micro-AB connector.
36  - One USB2.0 is connected to miniPCIe connector .
37- Ethernet:
38  - Supports SGMII 1G PHYs at Lane 2 and Lane 3
39  - Supports SFP+module with XFI retimers
40  - Supports AQR106/107 10G PHY with XFI/2.5G SGMII
41- PCIe and SATA:
42  - Mini PCIe express x1 (Gen1/2/3)card
43  - Standard PCIe x1 (Gen1/2/3) card
44  - Standard PCIe x1 (Gen1/2/3) card
45  - One SATA 3.0 connector
46
47Supported Features
48==================
49
50NXP LS1046A RDB board default configuration supports the following
51hardware features:
52
53+-----------+------------+--------------------------------------+
54| Interface | Controller | Driver/Component                     |
55+===========+============+======================================+
56| GIC-400   | on-chip    | GICv2 interrupt controller           |
57+-----------+------------+--------------------------------------+
58| ARM TIMER | on-chip    | System Clock                         |
59+-----------+------------+--------------------------------------+
60| UART      | on-chip    | NS16550 compatible serial port       |
61+-----------+------------+--------------------------------------+
62
63Other hardware features have not been enabled yet for this board.
64
65The default configuration can be found in the defconfig file for NON-SMP:
66
67    :zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig`
68
69Or for SMP running on all four CPU Cores:
70
71	:zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig`
72
73Or for SMP running on 2 CPU Cores (Core2 and Core3):
74
75	:zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig`
76
77There are two serial port on the board: uart1 and uart2, Zephyr is using
78uart2 as serial console.
79
80Programming and Debugging
81*************************
82
83Use the following configuration to run basic Zephyr applications and
84kernel tests on LS1046A RDB board. For example, with the :zephyr:code-sample:`synchronization` sample:
85
861. Non-SMP mode
87
88.. zephyr-app-commands::
89   :zephyr-app: samples/synchronization
90   :host-os: unix
91   :board: ls1046ardb
92   :goals: build
93
94This will build an image with the synchronization sample app.
95
96Use u-boot to load and kick Zephyr.bin to CPU Core0:
97
98.. code-block:: console
99
100	tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go  0xc0000000;
101
102Or kick Zephyr.bin to any other CPU Cores, for example run Zephyr on Core3:
103
104.. code-block:: console
105
106	tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 3 release 0xc0000000;
107
108
109It will display the following console output:
110
111.. code-block:: console
112
113	*** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7  ***
114	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
115	thread_b: Hello World from cpu 0 on nxp_ls1046ardb!
116	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
117
1182. SMP mode running on 4 CPU Cores
119
120.. zephyr-app-commands::
121   :zephyr-app: samples/synchronization
122   :host-os: unix
123   :board: ls1046ardb/ls1046a/smp/4cores
124   :goals: build
125
126This will build an image with the synchronization sample app.
127
128Use u-boot to load and kick Zephyr.bin to CPU Core0:
129
130.. code-block:: console
131
132	tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go  0xc0000000;
133
134It will display the following console output:
135
136.. code-block:: console
137
138	*** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7  ***
139	Secondary CPU core 1 (MPID:0x1) is up
140	Secondary CPU core 2 (MPID:0x2) is up
141	Secondary CPU core 3 (MPID:0x3) is up
142	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
143	thread_b: Hello World from cpu 1 on nxp_ls1046ardb!
144	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
145
1463. SMP mode running on 2 CPU Cores: Core2 and Core3
147
148.. zephyr-app-commands::
149   :zephyr-app: samples/synchronization
150   :host-os: unix
151   :board: ls1046ardb/ls1046a/smp
152   :goals: build
153
154This will build an image with the synchronization sample app.
155
156Use u-boot to load and kick Zephyr.bin to CPU Core2:
157
158.. code-block:: console
159
160	tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 2 release 0xc0000000;
161
162It will display the following console output:
163
164.. code-block:: console
165
166	*** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7  ***
167	Secondary CPU core 1 (MPID:0x3) is up
168	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
169	thread_b: Hello World from cpu 1 on nxp_ls1046ardb!
170	thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
171
1724. Running Zephyr on Jailhouse inmate Cell
173
174Use the following to run Zephyr in Jailhouse inmate, need to configure Jailhouse
175inmate Cell to use a single Core for Zephyr non-SMP mode, or use Core2 and Core3
176for Zephyr SMP 2cores image.
177
1781) Use root Cell dts to boot root Cell Linux.
179
1802) Install Jailhouse module:
181
182.. code-block:: console
183
184	modprobe jailhouse
185
1863) Run Zephyr demo in inmate Cell:
187
188.. code-block:: console
189
190	jailhouse enable ls1046a-rdb.cell
191	jailhouse cell create ls1046a-rdb-inmate-demo.cell
192	jailhouse cell load 1 zephyr.bin --address 0xc0000000
193	jailhouse cell start 1
194
195Flashing
196========
197
198Zephyr image can be loaded in DDR memory at address 0xc0000000 from SD Card,
199EMMC, QSPI Flash or downloaded from network in uboot.
200
201Debugging
202=========
203
204LS1046A RDB board includes one JTAG connector on board, connect it to
205CodeWarrior TAP for debugging.
206
207References
208==========
209
210`Layerscape LS1046A Reference Design Board <https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1046a-reference-design-board:LS1046A-RDB>`_
211
212`LS1046A Reference Manual <https://www.nxp.com/webapp/Download?colCode=LS1046ARM>`_
213