1 /* spi_pw.h - Penwell SPI driver definitions */ 2 3 /* 4 * Copyright (c) 2023 Intel Corporation. 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef ZEPHYR_DRIVERS_SPI_SPI_PW_H_ 10 #define ZEPHYR_DRIVERS_SPI_SPI_PW_H_ 11 12 #include "spi_context.h" 13 14 /* lpss penwell spi registers */ 15 #define PW_SPI_REG_CTRLR0 0x00 16 #define PW_SPI_REG_CTRLR1 0x04 17 #define PW_SPI_REG_SSSR 0x08 18 #define PW_SPI_REG_SSDR 0x10 19 #define PW_SPI_REG_SSTO 0x28 20 #define PW_SPI_REG_SITF 0x44 21 #define PW_SPI_REG_SIRF 0x48 22 23 #define PW_SPI_REG_CLKS 0x200 24 #define PW_SPI_REG_RESETS 0x204 25 #define PW_SPI_REG_ACTIVE_LTR 0x210 26 #define PW_SPI_REG_IDLE_LTR 0x217 27 #define PW_SPI_REG_TX_BIT_COUNT 0x218 28 #define PW_SPI_REG_RX_BIT_COUNT 0x21c 29 #define PW_SPI_REG_DMA_FINISH_DIS 0x220 30 31 #define PW_SPI_REG_CS_CTRL 0x224 32 #define PW_SPI_REG_SW_SCRATCH 0x228 33 #define PW_SPI_REG_CLK_GATE 0x238 34 #define PW_SPI_REG_REMAP_ADDR_LO 0x240 35 #define PW_SPI_REG_REMAP_ADDR_HI 0x244 36 #define PW_SPI_REG_DEV_IDLE_CTRL 0x24c 37 #define PW_SPI_REG_DEL_RX_CLK 0x250 38 #define PW_SPI_REG_CAP 0x2fc 39 40 /* CTRLR0 settings */ 41 #define PW_SPI_CTRLR0_SSE_BIT BIT(7) 42 #define PW_SPI_CTRLR0_EDSS_BIT BIT(20) 43 #define PW_SPI_CTRLR0_RIM_BIT BIT(22) 44 #define PW_SPI_CTRLR0_TIM_BIT BIT(23) 45 #define PW_SPI_CTRLR0_MOD_BIT BIT(31) 46 47 #define PW_SPI_CTRLR0_DATA_MASK (~(0xf << 0)) 48 #define PW_SPI_CTRLR0_EDSS_MASK (~(0x1 << 20)) 49 50 /* Data size set bits sscr0[3:0] */ 51 #define PW_SPI_DATA_SIZE_4_BIT 0x3 52 #define PW_SPI_DATA_SIZE_8_BIT 0x7 53 #define PW_SPI_DATA_SIZE_16_BIT 0xf 54 #define PW_SPI_DATA_SIZE_32_BIT (PW_SPI_CTRLR0_EDSS_BIT | \ 55 PW_SPI_DATA_SIZE_16_BIT) 56 /* Frame format sscr0[5:4] */ 57 #define PW_SPI_FRF_MOTOROLA (~(0x3 << 4)) 58 59 /* SSP Baud rate sscr0[19:8] */ 60 #define PW_SPI_BR_2MHZ 0x31 61 #define PW_SPI_BR_4MHZ 0x18 62 #define PW_SPI_BR_5MHZ 0x13 63 #define PW_SPI_BR_10MHZ 0x9 64 #define PW_SPI_BR_20MHZ 0x5 65 #define PW_SPI_BR_MAX_FRQ 20000000 /* 20 MHz */ 66 /* [19:8] 12 bits */ 67 #define PW_SPI_SCR_MASK (BIT_MASK(12) << 8) 68 #define PW_SPI_SCR_SHIFT 0x8 69 70 /* CTRLR1 settings */ 71 #define PW_SPI_CTRL1_RIE_BIT BIT(0) 72 #define PW_SPI_CTRL1_TIE_BIT BIT(1) 73 #define PW_SPI_CTRL1_LBM_BIT BIT(2) 74 #define PW_SPI_CTRL1_SPO_BIT BIT(3) 75 #define PW_SPI_CTRL1_SPH_BIT BIT(4) 76 #define PW_SPI_CTRL1_IFS_BIT BIT(16) 77 #define PW_SPI_CTRL1_TINTE_BIT BIT(19) 78 #define PW_SPI_CTRL1_RSRE_BIT BIT(20) 79 #define PW_SPI_CTRL1_TSRE_BIT BIT(21) 80 #define PW_SPI_CTRL1_TRAIL_BIT BIT(22) 81 #define PW_SPI_CTRL1_RWOT_BIT BIT(23) 82 83 /* [4:3] phase & polarity mask */ 84 #define PW_SPI_CTRL1_SPO_SPH_MASK (BIT_MASK(2) << 3) 85 86 /* Status Register */ 87 #define PW_SPI_SSSR_TNF_BIT BIT(2) 88 #define PW_SPI_SSSR_RNE_BIT BIT(3) 89 #define PW_SPI_SSSR_BSY_BIT BIT(4) 90 #define PW_SPI_SSSR_TFS_BIT BIT(5) 91 #define PW_SPI_SSSR_RFS_BIT BIT(6) 92 #define PW_SPI_SSSR_ROR_BIT BIT(7) 93 #define PW_SPI_SSSR_PINT_BIT BIT(18) 94 #define PW_SPI_SSSR_TINT_BIT BIT(19) 95 #define PW_SPI_SSSR_TUR_BIT BIT(21) 96 97 /* SPI Tx FIFO Higher Water Mark [5:0] */ 98 #define PW_SPI_SITF_HWM_1_ENTRY 0x1 99 #define PW_SPI_SITF_HWM_4_ENTRY 0x4 100 #define PW_SPI_SITF_HWM_8_ENTRY 0x8 101 #define PW_SPI_SITF_HWM_16_ENTRY 0x10 102 #define PW_SPI_SITF_HWM_32_ENTRY 0x20 103 #define PW_SPI_SITF_HWM_64_ENTRY 0x40 104 105 /* SPI Tx FIFO Lower Water Mark[13:8] */ 106 #define PW_SPI_SITF_LWM_2_ENTRY (BIT(0) << 8) 107 #define PW_SPI_SITF_LWM_3_ENTRY (BIT(1) << 8) 108 #define PW_SPI_SITF_LWM_4_ENTRY ((BIT(1) | BIT(0)) << 8) 109 110 /* SPI Tx FIFO Level SITF[21:16] */ 111 #define PW_SPI_SITF_SITFL_MASK (BIT_MASK(6) << 16) 112 113 #define PW_SPI_SITF_SITFL_SHIFT 0x10 114 115 /* SPI Rx FIFO water mark */ 116 #define PW_SPI_SIRF_WMRF_1_ENTRY 0x1 117 #define PW_SPI_SIRF_WMRF_2_ENTRY 0x2 118 #define PW_SPI_SIRF_WMRF_4_ENTRY 0x4 119 #define PW_SPI_SITF_WMRF_8_ENTRY 0x8 120 #define PW_SPI_SITF_WMRF_16_ENTRY 0x10 121 #define PW_SPI_SITF_WMRF_32_ENTRY 0x20 122 #define PW_SPI_SITF_WMRF_64_ENTRY 0x40 123 124 /* SPI Rx FIFO Level RITF[13:8] */ 125 #define PW_SPI_SIRF_SIRFL_MASK (BIT_MASK(6) << 8) 126 #define PW_SPI_SIRF_SIRFL_SHIFT 0x8 127 128 /* Threshold default value */ 129 #define PW_SPI_WM_MASK BIT_MASK(6) 130 #define PW_SPI_SITF_LWMTF_SHIFT 0x8 131 #define PW_SPI_SITF_LOW_WM_DFLT BIT(PW_SPI_SITF_LWMTF_SHIFT) 132 #define PW_SPI_SITF_HIGH_WM_DFLT 0x20 133 #define PW_SPI_SIRF_WM_DFLT 0x28 134 135 /* Clocks */ 136 #define PW_SPI_CLKS_EN_BIT BIT(0) 137 #define PW_SPI_CLKS_MVAL BIT(1) 138 #define PW_SPI_CLKS_NVAL BIT(16) 139 #define PW_SPI_CLKS_UPDATE_BIT BIT(31) 140 141 /* mval mask [15:1] */ 142 #define PW_SPI_CLKS_MVAL_MASK (BIT_MASK(15) << 1) 143 144 /* nval mask [30:16] */ 145 #define PW_SPI_CLKS_NVAL_MASK (BIT_MASK(15) << 16) 146 147 /* SPI chip select control */ 148 #define PW_SPI_CS_MODE_BIT 0 149 #define PW_SPI_CS_STATE_BIT 1 150 #define PW_SPI_CS0_POL_BIT 12 151 #define PW_SPI_CS1_POL_BIT 13 152 153 /* ssp interrupt error bits */ 154 #define PW_SPI_INTR_ERRORS_MASK (PW_SPI_SSSR_TUR_BIT | \ 155 PW_SPI_SSSR_ROR_BIT | \ 156 PW_SPI_SSSR_TINT_BIT) 157 158 /* ssp interrupt bits */ 159 #define PW_SPI_INTR_BITS (PW_SPI_CTRL1_TIE_BIT | \ 160 PW_SPI_CTRL1_RIE_BIT | \ 161 PW_SPI_CTRL1_TINTE_BIT) 162 163 #define PW_SPI_INTR_MASK_TX (~(PW_SPI_CTRL1_TIE_BIT | \ 164 PW_SPI_CTRL1_TINTE_BIT)) 165 166 #define PW_SPI_INTR_MASK_RX (PW_SPI_CTRL1_RIE_BIT) 167 168 /* SSP & DMA reset */ 169 #define PW_SPI_INST_RESET 0x7 170 171 /* Chip select control */ 172 #define PW_SPI_CS_CTRL_SW_MODE BIT(0) 173 #define PW_SPI_CS_HIGH BIT(1) 174 #define PW_SPI_CS_LOW (~(PW_SPI_CS_HIGH)) 175 #define PW_SPI_CS_CTRL_CS_MASK 0x3 176 #define PW_SPI_CS_EN_SHIFT 0x8 177 #define PW_SPI_CS0_SELECT (~(BIT(PW_SPI_CS_EN_SHIFT))) 178 #define PW_SPI_CS1_SELECT BIT(PW_SPI_CS_EN_SHIFT) 179 #define PW_SPI_CS_CTRL_HW_MODE (~(PW_SPI_CS_CTRL_SW_MODE)) 180 181 #define PW_SPI_WIDTH_8BITS 8 182 #define PW_SPI_FRAME_SIZE_1_BYTE 1 183 #define PW_SPI_FRAME_SIZE_2_BYTES 2 184 #define PW_SPI_FRAME_SIZE_4_BYTES 4 185 186 #define PW_SPI_CS1_OUTPUT_SELECT 1 187 188 enum spi_pw_spo_sph_mode { 189 SPI_PW_MODE0 = 0, 190 SPI_PW_MODE1, 191 SPI_PW_MODE2, 192 SPI_PW_MODE3, 193 }; 194 195 enum spi_pw_cs_mode { 196 CS_HW_MODE = 0, 197 CS_SW_MODE, 198 CS_GPIO_MODE, 199 }; 200 201 struct spi_pw_config { 202 uint32_t id; 203 #ifdef CONFIG_SPI_PW_INTERRUPT 204 void (*irq_config)(const struct device *dev); 205 #endif 206 uint32_t clock_freq; 207 uint8_t op_modes; 208 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) 209 struct pcie_dev *pcie; 210 #endif 211 }; 212 213 struct spi_pw_data { 214 DEVICE_MMIO_RAM; 215 struct spi_context ctx; 216 uint8_t dfs; 217 uint8_t fifo_diff; 218 uint8_t cs_mode; 219 uint8_t cs_output; 220 uint32_t id; 221 uint8_t fifo_depth; 222 }; 223 224 #endif /* ZEPHYR_DRIVERS_SPI_SPI_PW_H_ */ 225
