1/* 2 * Copyright (c) 2021 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8 9/* Macros for device tree declarations of npcx soc family */ 10#include <zephyr/dt-bindings/adc/adc.h> 11#include <zephyr/dt-bindings/clock/npcx_clock.h> 12#include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h> 13#include <zephyr/dt-bindings/gpio/gpio.h> 14#include <zephyr/dt-bindings/i2c/i2c.h> 15#include <zephyr/dt-bindings/i2c/npcx-i2c.h> 16#include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h> 17#include <zephyr/dt-bindings/pwm/pwm.h> 18#include <zephyr/dt-bindings/sensor/npcx_tach.h> 19#include <freq.h> 20 21/ { 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-m4f"; 29 reg = <0>; 30 }; 31 }; 32 33 def-io-conf-list { 34 compatible = "nuvoton,npcx-pinctrl-def"; 35 /* Change default functional pads to GPIOs 36 * no_spip - PIN95.97.A1.A3 37 * no_fpip - PIN96.A0.A2.A4 - Internal flash only 38 * no_pwrgd - PIN72 39 * no_lpc_espi - PIN46.47.51.52.53.54.55.57 40 * no_peci_en - PIN81 41 * npsl_in1_sl - PIND2 42 * npsl_in2_sl - PIN00 43 * no_ksi0-7 - PIN31.30.27.26.25.24.23.22 44 * no_ks000-17 - PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04. 45 * 82.83.03.B1 46 */ 47 pinmux = <>; 48 }; 49 50 /** Dummy pinctrl node. It will be initialized with defaults based on the SoC series. 51 * Then, the user can override the pin control options at the board level. 52 */ 53 pinctrl: pinctrl { 54 compatible = "nuvoton,npcx-pinctrl"; 55 status = "okay"; 56 }; 57 58 /* Dummy node of IOs that have leakage current. The user can override 59 * 'leak-gpios' prop. at board DT file to save more power consumption. 60 */ 61 power_leakage_io: power-leakage-io { 62 compatible = "nuvoton,npcx-leakage-io"; 63 status = "okay"; 64 }; 65 66 soc { 67 pcc: clock-controller@4000d000 { 68 compatible = "nuvoton,npcx-pcc"; 69 /* Cells for bus type, clock control reg and bit */ 70 #clock-cells = <3>; 71 /* First reg region is Power Management Controller */ 72 /* Second reg region is Core Domain Clock Generator */ 73 reg = <0x4000d000 0x2000 74 0x400b5000 0x2000>; 75 reg-names = "pmc", "cdcg"; 76 }; 77 78 scfg: scfg@400c3000 { 79 compatible = "nuvoton,npcx-scfg"; 80 /* First reg region is System Configuration Device */ 81 /* Second reg region is Debugger Interface Device */ 82 /* Third reg region is System Glue Device */ 83 reg = <0x400c3000 0x70 84 0x400c3070 0x30 85 0x400a5000 0x2000>; 86 reg-names = "scfg", "dbg", "glue"; 87 #alt-cells = <3>; 88 #lvol-cells = <2>; 89 }; 90 91 mdc: mdc@4000c000 { 92 compatible = "syscon"; 93 reg = <0x4000c000 0xa>; 94 reg-io-width = <1>; 95 }; 96 97 mdc_header: mdc@4000c00a { 98 compatible = "syscon"; 99 reg = <0x4000c00a 0x4>; 100 reg-io-width = <2>; 101 }; 102 103 miwu0: miwu@400bb000 { 104 compatible = "nuvoton,npcx-miwu"; 105 reg = <0x400bb000 0x2000>; 106 index = <0>; 107 #miwu-cells = <2>; 108 }; 109 110 miwu1: miwu@400bd000 { 111 compatible = "nuvoton,npcx-miwu"; 112 reg = <0x400bd000 0x2000>; 113 index = <1>; 114 #miwu-cells = <2>; 115 }; 116 117 miwu2: miwu@400bf000 { 118 compatible = "nuvoton,npcx-miwu"; 119 reg = <0x400bf000 0x2000>; 120 index = <2>; 121 #miwu-cells = <2>; 122 }; 123 124 gpio0: gpio@40081000 { 125 compatible = "nuvoton,npcx-gpio"; 126 reg = <0x40081000 0x2000>; 127 gpio-controller; 128 index = <0x0>; 129 #gpio-cells=<2>; 130 }; 131 132 gpio1: gpio@40083000 { 133 compatible = "nuvoton,npcx-gpio"; 134 reg = <0x40083000 0x2000>; 135 gpio-controller; 136 index = <0x1>; 137 #gpio-cells=<2>; 138 }; 139 140 gpio2: gpio@40085000 { 141 compatible = "nuvoton,npcx-gpio"; 142 reg = <0x40085000 0x2000>; 143 gpio-controller; 144 index = <0x2>; 145 #gpio-cells=<2>; 146 }; 147 148 gpio3: gpio@40087000 { 149 compatible = "nuvoton,npcx-gpio"; 150 reg = <0x40087000 0x2000>; 151 gpio-controller; 152 index = <0x3>; 153 #gpio-cells=<2>; 154 }; 155 156 gpio4: gpio@40089000 { 157 compatible = "nuvoton,npcx-gpio"; 158 reg = <0x40089000 0x2000>; 159 gpio-controller; 160 index = <0x4>; 161 #gpio-cells=<2>; 162 }; 163 164 gpio5: gpio@4008b000 { 165 compatible = "nuvoton,npcx-gpio"; 166 reg = <0x4008b000 0x2000>; 167 gpio-controller; 168 index = <0x5>; 169 #gpio-cells=<2>; 170 }; 171 172 gpio6: gpio@4008d000 { 173 compatible = "nuvoton,npcx-gpio"; 174 reg = <0x4008d000 0x2000>; 175 gpio-controller; 176 index = <0x6>; 177 #gpio-cells=<2>; 178 }; 179 180 gpio7: gpio@4008f000 { 181 compatible = "nuvoton,npcx-gpio"; 182 reg = <0x4008f000 0x2000>; 183 gpio-controller; 184 index = <0x7>; 185 #gpio-cells=<2>; 186 }; 187 188 gpio8: gpio@40091000 { 189 compatible = "nuvoton,npcx-gpio"; 190 reg = <0x40091000 0x2000>; 191 gpio-controller; 192 index = <0x8>; 193 #gpio-cells=<2>; 194 }; 195 196 gpio9: gpio@40093000 { 197 compatible = "nuvoton,npcx-gpio"; 198 reg = <0x40093000 0x2000>; 199 gpio-controller; 200 index = <0x9>; 201 #gpio-cells=<2>; 202 }; 203 204 gpioa: gpio@40095000 { 205 compatible = "nuvoton,npcx-gpio"; 206 reg = <0x40095000 0x2000>; 207 gpio-controller; 208 index = <0xA>; 209 #gpio-cells=<2>; 210 }; 211 212 gpiob: gpio@40097000 { 213 compatible = "nuvoton,npcx-gpio"; 214 reg = <0x40097000 0x2000>; 215 gpio-controller; 216 index = <0xB>; 217 #gpio-cells=<2>; 218 }; 219 220 gpioc: gpio@40099000 { 221 compatible = "nuvoton,npcx-gpio"; 222 reg = <0x40099000 0x2000>; 223 gpio-controller; 224 index = <0xC>; 225 #gpio-cells=<2>; 226 }; 227 228 gpiod: gpio@4009b000 { 229 compatible = "nuvoton,npcx-gpio"; 230 reg = <0x4009b000 0x2000>; 231 gpio-controller; 232 index = <0xD>; 233 #gpio-cells=<2>; 234 }; 235 236 gpioe: gpio@4009d000 { 237 compatible = "nuvoton,npcx-gpio"; 238 reg = <0x4009d000 0x2000>; 239 gpio-controller; 240 index = <0xE>; 241 #gpio-cells=<2>; 242 }; 243 244 gpiof: gpio@4009f000 { 245 compatible = "nuvoton,npcx-gpio"; 246 reg = <0x4009f000 0x2000>; 247 gpio-controller; 248 index = <0xF>; 249 #gpio-cells=<2>; 250 }; 251 252 pwm0: pwm@40080000 { 253 compatible = "nuvoton,npcx-pwm"; 254 reg = <0x40080000 0x2000>; 255 pwm-channel = <0>; 256 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 0>; 257 #pwm-cells = <3>; 258 status = "disabled"; 259 }; 260 261 pwm1: pwm@40082000 { 262 compatible = "nuvoton,npcx-pwm"; 263 reg = <0x40082000 0x2000>; 264 pwm-channel = <1>; 265 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 1>; 266 #pwm-cells = <3>; 267 status = "disabled"; 268 }; 269 270 pwm2: pwm@40084000 { 271 compatible = "nuvoton,npcx-pwm"; 272 reg = <0x40084000 0x2000>; 273 pwm-channel = <2>; 274 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 2>; 275 #pwm-cells = <3>; 276 status = "disabled"; 277 }; 278 279 pwm3: pwm@40086000 { 280 compatible = "nuvoton,npcx-pwm"; 281 reg = <0x40086000 0x2000>; 282 pwm-channel = <3>; 283 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 3>; 284 #pwm-cells = <3>; 285 status = "disabled"; 286 }; 287 288 pwm4: pwm@40088000 { 289 compatible = "nuvoton,npcx-pwm"; 290 reg = <0x40088000 0x2000>; 291 pwm-channel = <4>; 292 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 4>; 293 #pwm-cells = <3>; 294 status = "disabled"; 295 }; 296 297 pwm5: pwm@4008a000 { 298 compatible = "nuvoton,npcx-pwm"; 299 reg = <0x4008a000 0x2000>; 300 pwm-channel = <5>; 301 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 5>; 302 #pwm-cells = <3>; 303 status = "disabled"; 304 }; 305 306 pwm6: pwm@4008c000 { 307 compatible = "nuvoton,npcx-pwm"; 308 reg = <0x4008c000 0x2000>; 309 pwm-channel = <6>; 310 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 6>; 311 #pwm-cells = <3>; 312 status = "disabled"; 313 }; 314 315 pwm7: pwm@4008e000 { 316 compatible = "nuvoton,npcx-pwm"; 317 reg = <0x4008e000 0x2000>; 318 pwm-channel = <7>; 319 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 7>; 320 #pwm-cells = <3>; 321 status = "disabled"; 322 }; 323 324 adc0: adc@400d1000 { 325 compatible = "nuvoton,npcx-adc"; 326 #io-channel-cells = <1>; 327 reg = <0x400d1000 0x2000>; 328 interrupts = <10 3>; 329 clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 4>; 330 vref-mv = <2816>; 331 status = "disabled"; 332 }; 333 334 twd0: watchdog@400d8000 { 335 compatible = "nuvoton,npcx-watchdog"; 336 reg = <0x400d8000 0x2000>; 337 t0-out = <&wui_t0out>; 338 }; 339 340 espi0: espi@4000a000 { 341 compatible = "nuvoton,npcx-espi"; 342 reg = <0x4000a000 0x2000>; 343 interrupts = <18 3>; /* Interrupt for eSPI Bus */ 344 345 /* clocks for eSPI modules */ 346 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL6 7>; 347 /* WUI maps for eSPI signals */ 348 espi-rst-wui = <&wui_espi_rst>; 349 350 #address-cells = <1>; 351 #size-cells = <0>; 352 #vw-cells = <3>; 353 status = "disabled"; 354 }; 355 356 host_sub: lpc@400c1000 { 357 compatible = "nuvoton,npcx-host-sub"; 358 /* host sub-module register address & size */ 359 reg = <0x400c1000 0x2000 360 0x40010000 0x2000 361 0x4000e000 0x2000 362 0x400c7000 0x2000 363 0x400c9000 0x2000 364 0x400cb000 0x2000>; 365 reg-names = "mswc", "shm", "c2h", "kbc", "pm_acpi", 366 "pm_hcmd"; 367 368 /* host sub-module IRQ and priority */ 369 interrupts = <25 3>, /* KBC Input-Buf-Full (IBF) */ 370 <56 3>, /* KBC Output-Buf-Empty (OBE) */ 371 <26 3>, /* PMCH Input-Buf-Full (IBF) */ 372 <3 3>, /* PMCH Output-Buf-Empty (OBE) */ 373 <6 3>; /* Port80 FIFO Not Empty */ 374 interrupt-names = "kbc_ibf", "kbc_obe", "pmch_ibf", 375 "pmch_obe", "p80_fifo"; 376 377 /* WUI map for accessing host sub-modules */ 378 host-acc-wui = <&wui_host_acc>; 379 380 /* clocks for host sub-modules */ 381 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 3>, 382 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>, 383 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>, 384 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>, 385 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 7>; 386 }; 387 388 tach1: tach@400e1000 { 389 compatible = "nuvoton,npcx-tach"; 390 reg = <0x400e1000 0x2000>; 391 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 5>; 392 status = "disabled"; 393 }; 394 395 tach2: tach@400e3000 { 396 compatible = "nuvoton,npcx-tach"; 397 reg = <0x400e3000 0x2000>; 398 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 6>; 399 status = "disabled"; 400 }; 401 402 ps2_ctrl0: ps2@400b1000 { 403 compatible = "nuvoton,npcx-ps2-ctrl"; 404 reg = <0x400b1000 0x1000>; 405 interrupts = <21 4>; 406 clocks = <&pcc NPCX_CLOCK_BUS_FREERUN NPCX_PWDWN_CTL1 3>; 407 408 /* PS2 Channels - Please use them as PS2 node */ 409 ps2_channel0: io_ps2_channel0 { 410 compatible = "nuvoton,npcx-ps2-channel"; 411 channel = <0x00>; 412 status = "disabled"; 413 }; 414 415 ps2_channel1: io_ps2_channel1 { 416 compatible = "nuvoton,npcx-ps2-channel"; 417 channel = <0x01>; 418 status = "disabled"; 419 }; 420 421 ps2_channel2: io_ps2_channel2 { 422 compatible = "nuvoton,npcx-ps2-channel"; 423 channel = <0x02>; 424 status = "disabled"; 425 }; 426 427 ps2_channel3: io_ps2_channel3 { 428 compatible = "nuvoton,npcx-ps2-channel"; 429 channel = <0x03>; 430 status = "disabled"; 431 }; 432 }; 433 434 /* Dedicated Quad-SPI interface to access SPI flashes */ 435 qspi_fiu0: quadspi@40020000 { 436 compatible = "nuvoton,npcx-fiu-qspi"; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 reg = <0x40020000 0x2000>; 440 }; 441 442 peci0: peci@400d4000 { 443 compatible = "nuvoton,npcx-peci"; 444 reg = <0x400d4000 0x1000>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 interrupts = <4 4>; 448 clocks = <&pcc NPCX_CLOCK_BUS_FMCLK NPCX_PWDWN_CTL4 5>; 449 status = "disabled"; 450 }; 451 452 kbd: kbd@400a3000 { 453 compatible = "nuvoton,npcx-kbd"; 454 reg = <0x400a3000 0x2000>; 455 interrupts = <49 4>; 456 clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>; 457 wui-maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26 458 &wui_io25 &wui_io24 &wui_io23 &wui_io22>; 459 status = "disabled"; 460 }; 461 462 spip0: spi@400d2000 { 463 compatible = "nuvoton,npcx-spip"; 464 reg = <0x400d2000 0x1000>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 interrupts = <57 3>; 468 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL4 7>; 469 status = "disabled"; 470 471 }; 472 }; 473 474 soc-if { 475 /* Soc specific peripheral interface phandles which don't contain 476 * 'reg' prop. Please overwrite 'status' prop. to 'okay' if you 477 * want to switch the interface from io to specific peripheral. 478 */ 479 host_uart: io_host_uart { 480 compatible = "nuvoton,npcx-host-uart"; 481 status = "disabled"; 482 }; 483 484 i2c0_0: io_i2c_ctrl0_port0 { 485 compatible = "nuvoton,npcx-i2c-port"; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 port = <NPCX_I2C_CTRL_PORT(0, 0)>; 489 controller = <&i2c_ctrl0>; 490 status = "disabled"; 491 }; 492 493 i2c1_0: io_i2c_ctrl1_port0 { 494 compatible = "nuvoton,npcx-i2c-port"; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 port = <NPCX_I2C_CTRL_PORT(1, 0)>; 498 controller = <&i2c_ctrl1>; 499 status = "disabled"; 500 }; 501 502 i2c2_0: io_i2c_ctrl2_port0 { 503 compatible = "nuvoton,npcx-i2c-port"; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 port = <NPCX_I2C_CTRL_PORT(2, 0)>; 507 controller = <&i2c_ctrl2>; 508 status = "disabled"; 509 }; 510 511 i2c3_0: io_i2c_ctrl3_port0 { 512 compatible = "nuvoton,npcx-i2c-port"; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 port = <NPCX_I2C_CTRL_PORT(3, 0)>; 516 controller = <&i2c_ctrl3>; 517 status = "disabled"; 518 }; 519 520 i2c4_1: io_i2c_ctrl4_port1 { 521 compatible = "nuvoton,npcx-i2c-port"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 port = <NPCX_I2C_CTRL_PORT(4, 1)>; 525 controller = <&i2c_ctrl4>; 526 status = "disabled"; 527 }; 528 529 i2c5_0: io_i2c_ctrl5_port0 { 530 compatible = "nuvoton,npcx-i2c-port"; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 port = <NPCX_I2C_CTRL_PORT(5, 0)>; 534 controller = <&i2c_ctrl5>; 535 status = "disabled"; 536 }; 537 538 i2c5_1: io_i2c_ctrl5_port1 { 539 compatible = "nuvoton,npcx-i2c-port"; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 port = <NPCX_I2C_CTRL_PORT(5, 1)>; 543 controller = <&i2c_ctrl5>; 544 status = "disabled"; 545 }; 546 547 i2c6_0: io_i2c_ctrl6_port0 { 548 compatible = "nuvoton,npcx-i2c-port"; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 port = <NPCX_I2C_CTRL_PORT(6, 0)>; 552 controller = <&i2c_ctrl6>; 553 status = "disabled"; 554 }; 555 556 i2c6_1: io_i2c_ctrl6_port1 { 557 compatible = "nuvoton,npcx-i2c-port"; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 port = <NPCX_I2C_CTRL_PORT(6, 1)>; 561 controller = <&i2c_ctrl6>; 562 status = "disabled"; 563 }; 564 565 i2c7_0: io_i2c_ctrl7_port0 { 566 compatible = "nuvoton,npcx-i2c-port"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 port = <NPCX_I2C_CTRL_PORT(7, 0)>; 570 controller = <&i2c_ctrl7>; 571 status = "disabled"; 572 }; 573 574 power_ctrl_psl: power-ctrl-psl { 575 compatible = "nuvoton,npcx-power-psl"; 576 status = "disabled"; 577 }; 578 }; 579 580 soc-id { 581 compatible = "nuvoton,npcx-soc-id"; 582 family-id = <0x20>; 583 }; 584 585 booter-variant { 586 compatible = "nuvoton,npcx-booter-variant"; 587 }; 588}; 589 590&nvic { 591 arm,num-irq-priority-bits = <3>; 592}; 593
