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Searched refs:mdiv (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_agilex_ll.c56 uint32_t clk_psrc, mdiv, ref_clk; in get_clk_freq() local
77 mdiv = CLKMGR_PLLM_MDIV(mmio_read_32(pllm_reg)); in get_clk_freq()
78 ref_clk *= mdiv; in get_clk_freq()
Dclock_control_agilex5_ll.c22 uint32_t mdiv = 0U; in get_ref_clk() local
60 mdiv = CLKCTRL_PLLM_MDIV(pllm_val); in get_ref_clk()
61 ref_clk *= mdiv; in get_ref_clk()
/Zephyr-latest/soc/snps/hsdk/
DCMakeLists.txt7 # -mcpu=hs38_linux includes -matomic -mcode-density -mdiv-rem
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp.c1164 uint32_t mdiv; in dai_ssp_bclk_prepare_enable() local
1177 &mdiv, &need_ecs); in dai_ssp_bclk_prepare_enable()
1191 mdiv = ft[DAI_INTEL_SSP_DEFAULT_IDX].freq / ssp_plat_data->params.bclk_rate; in dai_ssp_bclk_prepare_enable()
1201 mdiv -= 1; in dai_ssp_bclk_prepare_enable()
1204 if (mdiv > (SSCR0_SCR_MASK >> 8)) { in dai_ssp_bclk_prepare_enable()
1205 LOG_ERR("divisor %d is not within SCR range", mdiv); in dai_ssp_bclk_prepare_enable()
1212 sscr0 |= SSCR0_SCR(mdiv); in dai_ssp_bclk_prepare_enable()