1 /* 2 * Copyright (c) 2021 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ 7 #define ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ 8 9 /* The "shim" block contains most of the general system control 10 * registers on cAVS platforms. While the base address changes, it 11 * has remained largely, but not perfectly, compatible between 12 * versions. 13 */ 14 15 #ifndef _ASMLANGUAGE 16 struct cavs_shim { 17 uint32_t skuid; 18 uint32_t _unused0[7]; 19 uint32_t dspwc_lo; 20 uint32_t dspwc_hi; 21 uint32_t dspwctcs; 22 uint32_t _unused1[1]; 23 uint32_t dspwct0c_lo; 24 uint32_t dspwct0c_hi; 25 uint32_t dspwct1c_lo; 26 uint32_t dspwct1c_hi; 27 uint32_t _unused2[14]; 28 uint32_t clkctl; 29 uint32_t clksts; 30 uint32_t _unused3[4]; 31 uint16_t pwrctl; 32 uint16_t pwrsts; 33 uint32_t lpsctl; 34 uint32_t lpsdmas0; 35 uint32_t lpsdmas1; 36 uint32_t spsreq; /* Offset: 0x00A0 */ 37 uint32_t ldoctl; /* Offset: 0x00A4 */ 38 uint32_t _unused4[2]; 39 uint32_t lpsalhss0; /* Offset: 0x00B0 */ 40 uint32_t lpsalhss1; /* Offset: 0x00B4 */ 41 uint32_t lpsalhss2; /* Offset: 0x00B8 */ 42 uint32_t lpsalhss3; /* Offset: 0x00BC */ 43 uint32_t _unused5[4]; 44 uint32_t l2mecs; /* Offset: 0x00D0 */ 45 uint32_t _unused6; 46 uint32_t _unused7[2]; 47 uint32_t ltrc; /* Offset: 0x00E0 */ 48 uint32_t _unused8[3]; 49 uint32_t dbgo; /* Offset: 0x00F0 */ 50 uint32_t svcfg; /* Offset: 0x00F4 */ 51 uint32_t _unused9[2]; 52 }; 53 54 #define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim)))) 55 56 #define ADSP_SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c)) 57 58 #define ADSP_DSPWC_OFFSET 0x20 59 #define ADSP_DSPWCTCS_OFFSET 0x28 60 #define ADSP_DSPWCT0C_OFFSET 0x30 61 #define ADSP_DSPWCT1C_OFFSET 0x38 62 #define ADSP_CLKCTL_OFFSET 0x78 63 #define ADSP_CLKSTS_OFFSET 0x7C 64 #define ADSP_PWRCTL_OFFSET 0x90 65 #define ADSP_PWRSTS_OFFSET 0x92 66 #define ADSP_LPSCTL_OFFSET 0x94 67 68 /* L2 Local Memory control (cAVS 1.8+) */ 69 struct cavs_l2lm { 70 uint32_t l2lmcap; 71 uint32_t l2lmpat; 72 uint32_t _unused0[2]; 73 uint32_t hspgctl0; 74 uint32_t hsrmctl0; 75 uint32_t hspgists0; 76 uint32_t _unused1; 77 uint32_t hspgctl1; 78 uint32_t hsrmctl1; 79 uint32_t hspgists1; 80 uint32_t _unused2[9]; 81 uint32_t lspgctl; 82 uint32_t lsrmctl; 83 uint32_t lspgists; 84 }; 85 86 #define CAVS_L2LM (*((volatile struct cavs_l2lm *)DT_REG_ADDR(DT_NODELABEL(l2lm)))) 87 88 /* Host memory window control. Not strictly part of the shim block. */ 89 struct cavs_win { 90 uint32_t dmwba; 91 uint32_t dmwlo; 92 }; 93 94 #define CAVS_WIN ((volatile struct cavs_win *)DT_REG_ADDR(DT_NODELABEL(win))) 95 96 #endif /* _ASMLANGUAGE */ 97 98 /* cAVS 1.8+ CLKCTL bits */ 99 #define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */ 100 #define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */ 101 #define CAVS_CLKCTL_RLROSCC BIT(29) /* Request LP RING oscillator */ 102 #define CAVS_CLKCTL_SLIMFDCGB BIT(25) /* Slimbus force dynamic clock gating*/ 103 #define CAVS_CLKCTL_TCPLCG(x) BIT(16 + x) /* Set bit: prevent clock gating on core x */ 104 #define CAVS_CLKCTL_SLIMCSS BIT(6) /* Slimbus clock (0: XTAL, 1: Audio) */ 105 #define CAVS_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */ 106 #define CAVS_CLKCTL_WOVCROSC BIT(3) /* WOVCRO select */ 107 #define CAVS_CLKCTL_OCS BIT(2) /* Oscillator clock (0: LP, 1: HP) */ 108 #define CAVS_CLKCTL_LMCS BIT(1) /* LP mem divisor (0: div/2, 1: div/4) */ 109 #define CAVS_CLKCTL_HMCS BIT(0) /* HP mem divisor (0: div/2, 1: div/4) */ 110 111 #define CAVS_PWRCTL_TCPDSPPG(x) BIT(x) 112 #define CAVS_PWRSTS_PDSPPGS(x) BIT(x) 113 114 #define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16) 115 #define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(16) 116 117 #define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) 118 #define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) 119 120 #define ADSP_DMWBA_ENABLE BIT(0) 121 #define ADSP_DMWBA_READONLY BIT(1) 122 123 #define ADSP_CLKCTL_OSC_SOURCE_MASK BIT_MASK(2) 124 #define ADSP_CLKCTL_OSC_REQUEST_MASK (~BIT_MASK(28)) 125 126 /** LDO Control */ 127 #define ADSP_DSPRA_ADDRESS (0x71A60) 128 #define ADSP_LPGPDMACxO_ADDRESS(x) (ADSP_DSPRA_ADDRESS + 0x0000 + 0x0002*(x)) 129 #define ADSP_DSPIOPO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x0008) 130 #define ADSP_GENO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x000C) 131 #define ADSP_DSPALHO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x0010) 132 133 134 #define DSP_INIT_IOPO ADSP_DSPIOPO_ADDRESS 135 #define IOPO_DMIC_FLAG BIT(0) 136 #define IOPO_DSPKOSEL_FLAG BIT(1) 137 #define IOPO_ANCOSEL_FLAG BIT(2) 138 #define IOPO_DMIXOSEL_FLAG BIT(3) 139 #define IOPO_SLIMOSEL_FLAG BIT(4) 140 #define IOPO_SNDWOSEL_FLAG BIT(5) 141 #define IOPO_SLIMDOSEL_FLAG BIT(20) 142 #define IOPO_I2SSEL_MASK (0x3F << 0x8) 143 144 #define DSP_INIT_GENO ADSP_GENO_ADDRESS 145 #define GENO_MDIVOSEL BIT(1) 146 #define GENO_DIOPTOSEL BIT(2) 147 148 #define DSPALHO_ASO_FLAG BIT(0) 149 #define DSPALHO_CSO_FLAG BIT(1) 150 #define DSPALHO_CFO_FLAG BIT(2) 151 152 #endif /* ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ */ 153
