Searched refs:line_size (Results 1 – 6 of 6) sorted by relevance
98 size_t line_size; in arch_dcache_flush_range() local103 line_size = arch_dcache_line_size_get(); in arch_dcache_flush_range()104 addr &= ~(line_size - 1); in arch_dcache_flush_range()108 addr += line_size; in arch_dcache_flush_range()116 size_t line_size; in arch_dcache_invd_range() local120 line_size = arch_dcache_line_size_get(); in arch_dcache_invd_range()126 if (end_addr & (line_size - 1)) { in arch_dcache_invd_range()127 end_addr &= ~(line_size - 1); in arch_dcache_invd_range()131 if (addr & (line_size - 1)) { in arch_dcache_invd_range()132 addr &= ~(line_size - 1); in arch_dcache_invd_range()[all …]
79 size_t line_size; in arm64_dcache_range() local87 line_size = arch_dcache_line_size_get(); in arm64_dcache_range()106 if (end_addr & (line_size - 1)) { in arm64_dcache_range()107 end_addr &= ~(line_size - 1); in arm64_dcache_range()111 if (start_addr & (line_size - 1)) { in arm64_dcache_range()112 start_addr &= ~(line_size - 1); in arm64_dcache_range()117 start_addr += line_size; in arm64_dcache_range()122 start_addr &= ~(line_size - 1); in arm64_dcache_range()133 start_addr += line_size; in arm64_dcache_range()
70 size_t line_size = sys_cache_data_line_size_get(); in arch_dcache_flush_range() local75 if (!dcache_available() || (size == 0U) || line_size == 0U) { in arch_dcache_flush_range()81 start_addr = ROUND_DOWN(start_addr, line_size); in arch_dcache_flush_range()97 start_addr += line_size; in arch_dcache_flush_range()107 size_t line_size = sys_cache_data_line_size_get(); in arch_dcache_invd_range() local112 if (!dcache_available() || (size == 0U) || line_size == 0U) { in arch_dcache_invd_range()116 start_addr = ROUND_DOWN(start_addr, line_size); in arch_dcache_invd_range()125 start_addr += line_size; in arch_dcache_invd_range()
90 size_t line_size = sys_cache_data_line_size_get(); in arch_dcache_flush_range() local94 if (line_size == 0U) { in arch_dcache_flush_range()98 end = ROUND_UP(end, line_size); in arch_dcache_flush_range()100 for (; start < end; start += line_size) { in arch_dcache_flush_range()
57 uint8_t line_size; member124 sets = l2_cache_cfg.size / (ways * l2_cache_cfg.line_size); in nds_l2_cache_all()131 index += l2_cache_cfg.line_size; in nds_l2_cache_all()170 align_addr = ROUND_DOWN(addr, l2_cache_cfg.line_size); in nds_l2_cache_range()176 align_addr += l2_cache_cfg.line_size; in nds_l2_cache_range()209 static ALWAYS_INLINE int nds_l2_cache_init(uint8_t line_size) in nds_l2_cache_init() argument236 l2_cache_cfg.line_size = line_size; in nds_l2_cache_init()
80 static ALWAYS_INLINE int nds_cctl_range_operations(void *addr, size_t size, int line_size, int cmd) in nds_cctl_range_operations() argument86 align_addr = ROUND_DOWN(addr, line_size); in nds_cctl_range_operations()96 align_addr += line_size; in nds_cctl_range_operations()102 align_addr += line_size; in nds_cctl_range_operations()519 unsigned long line_size; in andes_cache_init() local522 line_size = (csr_read(NDS_MICM_CFG) >> MICM_CFG_ISZ_SHIFT) & BIT_MASK(3); in andes_cache_init()524 if (line_size == 0) { in andes_cache_init()530 if (line_size <= 5) { in andes_cache_init()531 cache_cfg.instr_line_size = 1 << (line_size + 2); in andes_cache_init()547 line_size = (csr_read(NDS_MDCM_CFG) >> MDCM_CFG_DSZ_SHIFT) & BIT_MASK(3); in andes_cache_init()[all …]
