1/* 2 * Copyright (c) 2022 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/** 8 * @file 9 * @brief Linker command/script file 10 * 11 * Linker script for the intel_apl_adsp platform 12 */ 13 14OUTPUT_ARCH(xtensa) 15 16#include <zephyr/devicetree.h> 17#include <xtensa/config/core-isa.h> 18#include <zephyr/linker/sections.h> 19#include <adsp-vectors.h> 20#include <adsp_memory.h> 21 22#include <zephyr/linker/linker-defs.h> 23#include <zephyr/linker/linker-tool.h> 24 25ENTRY(rom_entry); 26 27/* DSP RAM regions (all of them) are mapped twice on the DSP. One 28 * mapping is set up to bypass the L1 cache, so it must be used when 29 * multiprocessor coherence is desired, where the latter mapping is 30 * best used for processor-local data (e.g. stacks) or shared data 31 * that is managed with explicit cache flush/invalidate operations. 32 * 33 * These macros will set up a segment start address correctly, 34 * including alignment to a cache line. Be sure to also emit the 35 * section to ">ram" or ">ucram" as appropriate, to prevent the linker 36 * from filling in 512MB of sparse zeros. 37 */ 38#ifdef CONFIG_KERNEL_COHERENCE 39#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29)) 40#ifdef CONFIG_MMU 41#define SEGSTART_CACHED RPO_SET(ALIGN(CONFIG_MMU_PAGE_SIZE), CONFIG_XTENSA_CACHED_REGION) 42#define SEGSTART_UNCACHED RPO_SET(ALIGN(CONFIG_MMU_PAGE_SIZE), CONFIG_XTENSA_UNCACHED_REGION) 43#else 44#define SEGSTART_CACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION) 45#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION) 46#endif 47#else 48#ifdef CONFIG_MMU 49#define SEGSTART_CACHED ALIGN(CONFIG_MMU_PAGE_SIZE) 50#define SEGSTART_UNCACHED ALIGN(CONFIG_MMU_PAGE_SIZE) 51#else 52#define SEGSTART_CACHED . 53#define SEGSTART_UNCACHED . 54#endif 55#define ucram ram 56#endif 57 58/* intlist.ld needs an IDT_LIST memory region */ 59#define IDT_BASE 0xe0000000 60#define IDT_SIZE 0x2000 61 62/* rimage module sections are C struct data, and thus flagged ALLOC. 63 * The xcc linker demands they be in a declared memory region even if 64 * the enclosing output section is (NOLOAD). Put them here. 65 */ 66#define NOLOAD_BASE 0x20000 67#define NOLOAD_SIZE 0x100000 68 69#ifdef CONFIG_MMU 70#define MMU_PAGE_ALIGN . = ALIGN(CONFIG_MMU_PAGE_SIZE); 71#define HDR_MMU_PAGE_ALIGN ALIGN(CONFIG_MMU_PAGE_SIZE) 72#define HDR_4K_OR_MMU_PAGE_ALIGN ALIGN(CONFIG_MMU_PAGE_SIZE) 73#else 74#define MMU_PAGE_ALIGN 75#define HDR_MMU_PAGE_ALIGN 76#define HDR_4K_OR_MMU_PAGE_ALIGN ALIGN(4096) 77#endif 78 79#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN 80 81MEMORY { 82 vector_base_text : 83 org = VECBASE_RESET_PADDR_SRAM, 84 len = MEM_VECBASE_LIT_SIZE 85 vector_int2_lit : 86 org = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 87 len = MEM_VECT_LIT_SIZE 88 vector_int2_text : 89 org = INTLEVEL2_VECTOR_PADDR_SRAM, 90 len = MEM_VECT_TEXT_SIZE 91 vector_int3_lit : 92 org = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 93 len = MEM_VECT_LIT_SIZE 94 vector_int3_text : 95 org = INTLEVEL3_VECTOR_PADDR_SRAM, 96 len = MEM_VECT_TEXT_SIZE 97 vector_int4_lit : 98 org = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 99 len = MEM_VECT_LIT_SIZE 100 vector_int4_text : 101 org = INTLEVEL4_VECTOR_PADDR_SRAM, 102 len = MEM_VECT_TEXT_SIZE 103 vector_int7_lit : 104 org = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 105 len = MEM_VECT_LIT_SIZE 106 vector_int7_text : 107 org = INTLEVEL7_VECTOR_PADDR_SRAM, 108 len = MEM_VECT_TEXT_SIZE 109 vector_kernel_lit : 110 org = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 111 len = MEM_VECT_LIT_SIZE 112 vector_kernel_text : 113 org = KERNEL_VECTOR_PADDR_SRAM, 114 len = MEM_VECT_TEXT_SIZE 115 vector_user_lit : 116 org = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 117 len = MEM_VECT_LIT_SIZE 118 vector_user_text : 119 org = USER_VECTOR_PADDR_SRAM, 120 len = MEM_VECT_TEXT_SIZE 121 vector_double_lit : 122 org = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 123 len = MEM_VECT_LIT_SIZE 124 vector_double_text : 125 org = DOUBLEEXC_VECTOR_PADDR_SRAM, 126 len = MEM_VECT_TEXT_SIZE 127#ifdef CONFIG_XTENSA_MMU 128 xtensa_vector_code : 129 org = DOUBLEEXC_VECTOR_PADDR_SRAM + MEM_VECT_TEXT_SIZE, 130 len = RAM_BASE - (DOUBLEEXC_VECTOR_PADDR_SRAM + MEM_VECT_TEXT_SIZE) 131#endif 132 imr : 133 org = IMR_BOOT_LDR_TEXT_ENTRY_BASE, 134 len = 0x100000 135 ram : 136 org = RAM_BASE, 137 len = RAM_SIZE 138#ifdef CONFIG_KERNEL_COHERENCE 139 ucram : 140 org = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION), 141 len = RAM_SIZE 142#endif 143#ifdef CONFIG_GEN_ISR_TABLES 144 IDT_LIST : 145 org = IDT_BASE, 146 len = IDT_SIZE 147#endif 148 lpram : 149 org = LP_SRAM_BASE, 150 len = LP_SRAM_SIZE 151 noload : 152 org = NOLOAD_BASE, 153 len = NOLOAD_SIZE 154} 155 156SECTIONS { 157 158 /* Boot loader code in IMR memory */ 159 .imr : { 160 _imr_start = .; 161 /* Entry point MUST be here per external configuration */ 162 KEEP (*(.boot_entry.text)) 163 *(.imr .imr.*) 164 } >imr 165 166 /* Boot loader data. Note that rimage seems to want this 167 * page-aligned or it will throw an error, not sure why since all 168 * the ROM cares about is a contiguous region. And it's 169 * particularly infuriating as it precludes linker .rodata next to 170 * .text. 171 */ 172 .imrdata : ALIGN(4096) { 173 *(.imrdata .imrdata.*) 174 } >imr 175 176 /* Cold code in IMR memory */ 177 .cold : ALIGN(4096) { 178 __cold_start = .; 179 *(.cold .cold.* ) 180 __cold_end = .; 181 } >imr 182 183 /* Cold data. */ 184 .coldrodata : ALIGN(4096) { 185 __coldrodata_start = .; 186 *(.coldrodata .coldrodata.*) 187 _imr_end = .; 188 } >imr 189 190 .WindowVectors.text : { 191 _WindowVectors_text_start = .; 192 KEEP (*(.WindowVectors.text)) 193 _WindowVectors_text_end = .; 194 } >vector_base_text 195 .Level2InterruptVector.literal : { 196 _Level2InterruptVector_literal_start = .; 197 *(.Level2InterruptVector.literal) 198 _Level2InterruptVector_literal_end = .; 199 } >vector_int2_lit 200 .Level2InterruptVector.text : { 201 _Level2InterruptVector_text_start = .; 202 KEEP (*(.Level2InterruptVector.text)) 203 _Level2InterruptVector_text_end = .; 204 } >vector_int2_text 205 .Level3InterruptVector.literal : { 206 _Level3InterruptVector_literal_start = .; 207 *(.Level3InterruptVector.literal) 208 _Level3InterruptVector_literal_end = .; 209 } >vector_int3_lit 210 .Level3InterruptVector.text : { 211 _Level3InterruptVector_text_start = .; 212 KEEP (*(.Level3InterruptVector.text)) 213 _Level3InterruptVector_text_end = .; 214 } >vector_int3_text 215 .Level4InterruptVector.literal : { 216 _Level4InterruptVector_literal_start = .; 217 *(.Level4InterruptVector.literal) 218 _Level4InterruptVector_literal_end = .; 219 } >vector_int4_lit 220 .Level4InterruptVector.text : { 221 _Level4InterruptVector_text_start = .; 222 KEEP (*(.Level4InterruptVector.text)) 223 _Level4InterruptVector_text_end = .; 224 } >vector_int4_text 225 .DebugExceptionVector.literal : { 226 _DebugExceptionVector_literal_start = .; 227 *(.DebugExceptionVector.literal) 228 _DebugExceptionVector_literal_end = .; 229 } >vector_int4_lit 230 .DebugExceptionVector.text : { 231 _DebugExceptionVector_text_start = .; 232 KEEP (*(.DebugExceptionVector.text)) 233 _DebugExceptionVector_text_end = .; 234 } >vector_int4_text 235 .NMIExceptionVector.literal : { 236 _NMIExceptionVector_literal_start = .; 237 *(.NMIExceptionVector.literal) 238 _NMIExceptionVector_literal_end = .; 239 } >vector_int7_lit 240 .NMIExceptionVector.text : { 241 _NMIExceptionVector_text_start = .; 242 KEEP (*(.NMIExceptionVector.text)) 243 _NMIExceptionVector_text_end = .; 244 } >vector_int7_text 245 .KernelExceptionVector.literal : { 246 _KernelExceptionVector_literal_start = .; 247 *(.KernelExceptionVector.literal) 248 _KernelExceptionVector_literal_end = .; 249 } >vector_kernel_lit 250 .KernelExceptionVector.text : { 251 _KernelExceptionVector_text_start = .; 252 KEEP (*(.KernelExceptionVector.text)) 253 _KernelExceptionVector_text_end = .; 254 } >vector_kernel_text 255 .UserExceptionVector.literal : { 256 _UserExceptionVector_literal_start = .; 257 *(.UserExceptionVector.literal) 258 _UserExceptionVector_literal_end = .; 259 } >vector_user_lit 260 .UserExceptionVector.text : { 261 _UserExceptionVector_text_start = .; 262 KEEP (*(.UserExceptionVector.text)) 263 _UserExceptionVector_text_end = .; 264 } >vector_user_text 265 .DoubleExceptionVector.literal : { 266 _DoubleExceptionVector_literal_start = .; 267 *(.DoubleExceptionVector.literal) 268 _DoubleExceptionVector_literal_end = .; 269 } >vector_double_lit 270 .DoubleExceptionVector.text : { 271 _DoubleExceptionVector_text_start = .; 272 KEEP (*(.DoubleExceptionVector.text)) 273 _DoubleExceptionVector_text_end = .; 274 } >vector_double_text 275 276#ifdef CONFIG_XTENSA_MMU 277 .xtensa_vector_code : { 278 /* There is not much space between .DoubleExceptionVector 279 * and the beginning of .text. So need to be careful on 280 * what to put in this section. It would mostly be things 281 * that are required to handle exceptions and interrupts. 282 * Also things we want to avoid TLB misses during exception 283 * handling. 284 */ 285 286 *libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.literal) 287 *libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.iram.text) 288 *libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.text) 289 290 *libarch__xtensa__core.a:window_vectors.S.obj(.iram.text) 291 292 /* For _Level1Vector */ 293 *libarch__xtensa__core.a:vector_handlers_util.S.obj(.iram0.text) 294 295 *libarch__xtensa__core.a:vector_handlers.c.obj(.literal.xtensa_int?_c) 296 *libarch__xtensa__core.a:vector_handlers.c.obj(.text.xtensa_int?_c) 297 298 *libarch__xtensa__core.a:userspace.S.obj(.literal.xtensa_do_syscall) 299 *libarch__xtensa__core.a:userspace.S.obj(.text.xtensa_do_syscall) 300 301#ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER 302 *libarch__xtensa__core.a:syscall_helper.c.obj(.text.xtensa_syscall_helper*) 303#endif /* CONFIG_XTENSA_SYSCALL_USE_HELPER */ 304 305 } > xtensa_vector_code 306#endif /* CONFIG_XTENSA_MMU */ 307 308 .text : HDR_MMU_PAGE_ALIGN 309 { 310 __text_region_start = .; 311 _image_ram_start = .; 312 z_mapped_start = .; 313 *(.iram1 .iram1.*) 314 *(.entry.text) 315 *(.init.literal) 316 *(.iram0.text) 317 318#ifdef CONFIG_XTENSA_MMU 319 /* 320 * The C handle blows up in size significantly when logging is enabled. 321 * So we can't keep this in .xtensa_vector_code above. Though we try to 322 * leep these close enough that, hopefully, we can avoid TLB misses. 323 */ 324 *libarch__xtensa__core.a:vector_handlers.c.obj(.literal.xtensa_excint1_c) 325 *libarch__xtensa__core.a:vector_handlers.c.obj(.text.xtensa_excint1_c) 326 327 /* 328 * Experiment shows that system would not boot if this is away from 329 * VECBASE more than a few pages. So workaround the issue by putting 330 * xtensa_mmu_init() here. 331 */ 332 *libarch__xtensa__core.a:ptables.c.obj(.literal.xtensa_mmu_init) 333 *libarch__xtensa__core.a:ptables.c.obj(.text.xtensa_mmu_init) 334#endif 335 336 KEEP(*(.init)) 337 KEEP(*(.lps_vector)) 338 *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) 339 MMU_PAGE_ALIGN 340 *(.literal .text) 341 *(.literal.* .text.*) 342 *(.fini.literal) 343 KEEP(*(.fini)) 344 *(.gnu.version) 345#include <zephyr/linker/kobject-text.ld> 346 MMU_PAGE_ALIGN 347 __text_region_end = .; 348 } >ram 349 350 .rodata : HDR_4K_OR_MMU_PAGE_ALIGN 351 { 352 __rodata_region_start = .; 353 *(.rodata) 354 *(.rodata.*) 355 *(.gnu.linkonce.r.*) 356 *(.rodata1) 357 358 . = ALIGN(4); 359 #include <snippets-rodata.ld> 360 #include <zephyr/linker/kobject-rom.ld> 361 362 __XT_EXCEPTION_TABLE__ = .; 363 KEEP (*(.xt_except_table)) 364 KEEP (*(.gcc_except_table .gcc_except_table.*)) 365 *(.gnu.linkonce.e.*) 366 *(.gnu.version_r) 367 KEEP (*(.eh_frame)) 368 KEEP (*crtbegin.o(.ctors)) 369 KEEP (*crtbegin.o(.dtors)) 370 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 371 KEEP (*(SORT(.dtors.*))) 372 KEEP (*(.dtors)) 373 __XT_EXCEPTION_DESCS__ = .; 374 *(.xt_except_desc) 375 *(.gnu.linkonce.h.*) 376 __XT_EXCEPTION_DESCS_END__ = .; 377 *(.xt_except_desc_end) 378 *(.dynamic) 379 *(.gnu.version_d) 380 _bss_table_start = .; 381 LONG(_bss_start) 382 LONG(_bss_end) 383 _bss_table_end = .; 384 MMU_PAGE_ALIGN 385 } >ram 386 387 .module_init : HDR_MMU_PAGE_ALIGN { 388 _module_init_start = .; 389 *(*.initcall) 390 _module_init_end = .; 391 } >ram 392 393#define RAMABLE_REGION ram 394#define ROMABLE_REGION ram 395 396 __common_rom_region_start = SEGSTART_CACHED; 397#include <zephyr/linker/common-rom.ld> 398/* Located in generated directory. This file is populated by calling 399 * zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs. 400 */ 401#include <snippets-rom-sections.ld> 402 __rodata_region_end = .; 403 __common_rom_region_end = .; 404 __rodata_region_end = .; 405 406 .noinit SEGSTART_UNCACHED : HDR_MMU_PAGE_ALIGN { 407 __data_start = .; 408 *(.noinit) 409 *(.noinit.*) 410 } >ucram 411 412#include <zephyr/linker/kobject-priv-stacks.ld> 413 . = SEGSTART_UNCACHED; 414 415 .data SEGSTART_UNCACHED : HDR_MMU_PAGE_ALIGN { 416 *(.data) 417 *(.data.*) 418 *(.gnu.linkonce.d.*) 419 KEEP(*(.gnu.linkonce.d.*personality*)) 420 *(.data1) 421 *(.sdata) 422 *(.sdata.*) 423 *(.gnu.linkonce.s.*) 424 *(.sdata2) 425 *(.sdata2.*) 426 *(.gnu.linkonce.s2.*) 427 KEEP(*(.jcr)) 428 _trace_ctx_start = ABSOLUTE(.); 429 *(.trace_ctx) 430 _trace_ctx_end = ABSOLUTE(.); 431 *(.gna_model) 432 __data_end = .; 433 MMU_PAGE_ALIGN 434 } >ucram 435 436 .lit4 SEGSTART_CACHED : { 437 _lit4_start = .; 438 *(*.lit4) 439 *(.lit4.*) 440 *(.gnu.linkonce.lit4.*) 441 _lit4_end = .; 442 } >ram 443 444/* These values need to change in our scheme, where the common-ram 445 * sections need to be linked in safe/uncached memory but common-rom 446 * wants to use the cache 447 */ 448. = SEGSTART_UNCACHED; 449#undef RAMABLE_REGION 450#undef ROMABLE_REGION 451#define RAMABLE_REGION ucram 452#define ROMABLE_REGION ucram 453 454 .fw_ready SEGSTART_UNCACHED : { 455 KEEP(*(".fw_ready")); 456 KEEP (*(.fw_ready_metadata)) 457 } > ucram 458 459 __common_ram_region_start = .; 460 461#ifdef CONFIG_USERSPACE 462 463#define APP_SHARED_ALIGN MMU_PAGE_ALIGN 464#define EMPTY_APP_SHARED_ALIGN APP_SHARED_ALIGN 465 466 /* APP SHARED MEMORY REGION */ 467#include <app_smem.ld> 468 _app_smem_size = _app_smem_end - _app_smem_start; 469 _app_smem_num_words = _app_smem_size >> 2; 470 _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME); 471#endif /* CONFIG_USERSPACE */ 472 473#include <zephyr/linker/common-ram.ld> 474#include <zephyr/linker/kobject-data.ld> 475 __common_ram_region_end = .; 476 477 .tm_clone_table : { 478 *(.tm_clone_table) 479 } >ram 480 481 /* This section is cached. By default it contains only declared 482 * thread stacks, but applications can put symbols here too. 483 */ 484 .cached SEGSTART_CACHED : { 485 _cached_start = .; 486 *(.cached .cached.*) 487#ifdef CONFIG_USERSPACE 488 z_user_stacks_start = .; 489 *(.user_stacks*) 490 z_user_stacks_end = .; 491#endif 492 _cached_end = .; 493 } >ram 494 495 /* Rimage requires 4k alignment between "DATA" and "BSS", can't do 496 * this in the section declaration below because we're also changing 497 * cacheability and that leaves a gap in the image large enough for 498 * binutils to decide to warn about (no way to turn that off, it 499 * seems, --warn-section-align is on by default) 500 */ 501 . = ALIGN(4096); 502 503 .bss SEGSTART_UNCACHED (NOLOAD) : 504 { 505 _bss_start = .; 506 *(.dynsbss) 507 *(.sbss) 508 *(.sbss.*) 509 *(.gnu.linkonce.sb.*) 510 *(.scommon) 511 *(.sbss2) 512 *(.sbss2.*) 513 *(.gnu.linkonce.sb2.*) 514 *(.dynbss) 515 *(.bss) 516 *(.bss.*) 517 *(.gnu.linkonce.b.*) 518 *(COMMON) 519 . = ALIGN(8); 520 MMU_PAGE_ALIGN 521 _bss_end = .; 522 } >ucram 523 524 . = SEGSTART_UNCACHED; 525 _end = ALIGN(8); 526 527 /* Heap start and end markers. Used to reserve system heap memory. */ 528 .heap_mem SEGSTART_UNCACHED (NOLOAD) : 529 { 530 _heap_start = .; 531 *(.heap_mem) 532 } >ucram 533 534 .unused_ram_start_marker SEGSTART_CACHED (NOLOAD) : 535 { 536 . = ALIGN(4096); 537 _unused_ram_start_marker = .; 538 *(.unused_ram_start_marker) 539 *(.unused_ram_start_marker.*) 540 z_mapped_end = .; 541 } >ram 542 543 /* Heap start and end markers. Used with libc malloc code. */ 544 . = SEGSTART_UNCACHED; 545 _end = ALIGN(8); 546 . = SEGSTART_CACHED; 547 z_mapped_end = .; 548 . = L2_SRAM_BASE + L2_SRAM_SIZE; 549 . = SEGSTART_UNCACHED; 550 _heap_end = .; 551 _heap_sentry = .; 552 . = SEGSTART_CACHED; 553 _image_ram_end = .; 554 555 /* dma buffers */ 556 .lpbuf (NOLOAD): { 557 _dma_buf_start = .; 558 *(.dma_buffers) 559 _dma_buf_end = .; 560 } >lpram 561 562 /* Non-loadable sections below. Back to cached memory so 563 * the cache remap script doesn't try to move them around needlessly. 564 */ 565 . = SEGSTART_CACHED; 566 567 /* rimage module manifest headers */ 568 .module.boot : { KEEP(*(.module.boot)) } >noload 569 .module.cold : { KEEP(*(.module.cold)) } >noload 570 .module.main : { KEEP(*(.module.main)) } >noload 571 572 .static_uuid_entries : { 573 *(*.static_uuids) 574 } >noload 575 576 .static_log_entries : { 577 *(*.static_log*) 578 } >noload 579 580 /* This is the "extended manifest" data (mostly versioning stuff) 581 * emitted by SOF and inspected by the kernel driver. It doesn't 582 * appear directly in the image, but rimage will parse and repack 583 * this into the output file header, so requires this be present 584 * even if empty. Alignment and padding to 16 bytes is required, 585 * otherwise rimage will complain about the size being wrong (which 586 * sounds like a struct should be declared packed somewhere...) 587 */ 588 .fw_metadata : ALIGN(16) { 589 KEEP (*(.fw_metadata)) 590 . = ALIGN(16); 591 } >noload 592 593#include <snippets-sections.ld> 594 595#include <zephyr/linker/debug-sections.ld> 596 597 /DISCARD/ : { *(.note.GNU-stack) } 598 599 .xtensa.info 0 : { *(.xtensa.info) } 600 .xt.insn 0 : { 601 KEEP (*(.xt.insn)) 602 KEEP (*(.gnu.linkonce.x.*)) 603 } 604 .xt.prop 0 : { 605 KEEP (*(.xt.prop)) 606 KEEP (*(.xt.prop.*)) 607 KEEP (*(.gnu.linkonce.prop.*)) 608 } 609 .xt.lit 0 : { 610 KEEP (*(.xt.lit)) 611 KEEP (*(.xt.lit.*)) 612 KEEP (*(.gnu.linkonce.p.*)) 613 } 614 .xt.profile_range 0 : { 615 KEEP (*(.xt.profile_range)) 616 KEEP (*(.gnu.linkonce.profile_range.*)) 617 } 618 .xt.profile_ranges 0 : { 619 KEEP (*(.xt.profile_ranges)) 620 KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) 621 } 622 .xt.profile_files 0 : { 623 KEEP (*(.xt.profile_files)) 624 KEEP (*(.gnu.linkonce.xt.profile_files.*)) 625 } 626 627#ifdef CONFIG_GEN_ISR_TABLES 628#include <zephyr/linker/intlist.ld> 629#endif 630 631#ifdef CONFIG_LLEXT 632#include <zephyr/linker/llext-sections.ld> 633#endif 634} 635
