1 /*
2 * Copyright (c) 2024-2025 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "udc_common.h"
8
9 #include <soc.h>
10 #include <zephyr/drivers/pinctrl.h>
11 #include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
12 #include <zephyr/drivers/usb/udc.h>
13 #include "r_usb_device.h"
14
15 #include <zephyr/logging/log.h>
16 LOG_MODULE_REGISTER(udc_renesas_ra, CONFIG_UDC_DRIVER_LOG_LEVEL);
17
18 struct udc_renesas_ra_config {
19 const struct pinctrl_dev_config *pcfg;
20 const struct device **clocks;
21 size_t num_of_clocks;
22 size_t num_of_eps;
23 struct udc_ep_config *ep_cfg_in;
24 struct udc_ep_config *ep_cfg_out;
25 void (*make_thread)(const struct device *dev);
26 int speed_idx;
27 };
28
29 struct udc_renesas_ra_data {
30 struct k_thread thread_data;
31 struct st_usbd_instance_ctrl udc;
32 struct st_usbd_cfg udc_cfg;
33 };
34
35 enum udc_renesas_ra_event_type {
36 /* An event generated by the HAL driver */
37 UDC_RENESAS_RA_EVT_HAL,
38 /* Shim driver event to trigger next transfer */
39 UDC_RENESAS_RA_EVT_XFER,
40 /* Let controller perform status stage */
41 UDC_RENESAS_RA_EVT_STATUS,
42 };
43
44 struct udc_renesas_ra_evt {
45 enum udc_renesas_ra_event_type type;
46 usbd_event_t hal_evt;
47 uint8_t ep;
48 };
49
50 K_MSGQ_DEFINE(drv_msgq, sizeof(struct udc_renesas_ra_evt), CONFIG_UDC_RENESAS_RA_MAX_QMESSAGES,
51 sizeof(uint32_t));
52
53 extern void usb_device_isr(void);
54
udc_renesas_ra_event_handler(usbd_callback_arg_t * p_args)55 static void udc_renesas_ra_event_handler(usbd_callback_arg_t *p_args)
56 {
57 const struct device *dev = p_args->p_context;
58 struct udc_renesas_ra_evt evt;
59
60 switch (p_args->event.event_id) {
61 case USBD_EVENT_BUS_RESET:
62 udc_submit_event(dev, UDC_EVT_RESET, 0);
63 break;
64
65 case USBD_EVENT_VBUS_RDY:
66 udc_submit_event(dev, UDC_EVT_VBUS_READY, 0);
67 break;
68
69 case USBD_EVENT_VBUS_REMOVED:
70 udc_submit_event(dev, UDC_EVT_VBUS_REMOVED, 0);
71 break;
72
73 case USBD_EVENT_SUSPEND:
74 udc_submit_event(dev, UDC_EVT_SUSPEND, 0);
75 break;
76
77 case USBD_EVENT_RESUME:
78 udc_submit_event(dev, UDC_EVT_RESUME, 0);
79 break;
80
81 case USBD_EVENT_SOF:
82 udc_submit_event(dev, UDC_EVT_SOF, 0);
83 break;
84
85 default:
86 evt.type = UDC_RENESAS_RA_EVT_HAL;
87 evt.hal_evt = p_args->event;
88 k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
89 break;
90 }
91 }
92
udc_renesas_ra_interrupt_handler(void * arg)93 static void udc_renesas_ra_interrupt_handler(void *arg)
94 {
95 ARG_UNUSED(arg);
96 usb_device_isr();
97 }
98
udc_event_xfer_next(const struct device * dev,const uint8_t ep)99 static void udc_event_xfer_next(const struct device *dev, const uint8_t ep)
100 {
101 struct udc_renesas_ra_data *data = udc_get_private(dev);
102 struct net_buf *buf;
103
104 if (udc_ep_is_busy(dev, ep)) {
105 return;
106 }
107
108 buf = udc_buf_peek(dev, ep);
109 if (buf != NULL) {
110 int err;
111
112 if (USB_EP_DIR_IS_IN(ep)) {
113 err = R_USBD_XferStart(&data->udc, ep, buf->data, buf->len);
114 } else {
115 err = R_USBD_XferStart(&data->udc, ep, buf->data, buf->size);
116 }
117
118 if (err != FSP_SUCCESS) {
119 LOG_ERR("ep 0x%02x error", ep);
120 udc_submit_ep_event(dev, buf, -ECONNREFUSED);
121 } else {
122 udc_ep_set_busy(dev, ep, true);
123 }
124 }
125 }
126
usbd_ctrl_feed_dout(const struct device * dev,const size_t length)127 static int usbd_ctrl_feed_dout(const struct device *dev, const size_t length)
128 {
129 struct udc_ep_config *cfg = udc_get_ep_cfg(dev, USB_CONTROL_EP_OUT);
130 struct net_buf *buf;
131 struct udc_renesas_ra_data *data = udc_get_private(dev);
132
133 buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, length);
134 if (buf == NULL) {
135 return -ENOMEM;
136 }
137
138 k_fifo_put(&cfg->fifo, buf);
139
140 if (FSP_SUCCESS != R_USBD_XferStart(&data->udc, cfg->addr, buf->data, buf->size)) {
141 return -EIO;
142 }
143
144 return 0;
145 }
146
udc_event_xfer_setup(const struct device * dev,struct udc_renesas_ra_evt * evt)147 static int udc_event_xfer_setup(const struct device *dev, struct udc_renesas_ra_evt *evt)
148 {
149 struct net_buf *buf;
150 int err;
151
152 struct usb_setup_packet *setup_packet =
153 (struct usb_setup_packet *)&evt->hal_evt.setup_received;
154
155 buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, sizeof(struct usb_setup_packet));
156 if (buf == NULL) {
157 LOG_ERR("Failed to allocate for setup");
158 return -ENOMEM;
159 }
160
161 udc_ep_buf_set_setup(buf);
162 net_buf_add_mem(buf, setup_packet, sizeof(struct usb_setup_packet));
163
164 /* Update to next stage of control transfer */
165 udc_ctrl_update_stage(dev, buf);
166
167 if (udc_ctrl_stage_is_data_out(dev)) {
168 /* Allocate and feed buffer for data OUT stage */
169 LOG_DBG("s:%p|feed for -out-", buf);
170 err = usbd_ctrl_feed_dout(dev, udc_data_stage_length(buf));
171 if (err == -ENOMEM) {
172 err = udc_submit_ep_event(dev, buf, err);
173 }
174 } else if (udc_ctrl_stage_is_data_in(dev)) {
175 err = udc_ctrl_submit_s_in_status(dev);
176 } else {
177 err = udc_ctrl_submit_s_status(dev);
178 }
179
180 return err;
181 }
182
udc_event_xfer_ctrl_in(const struct device * dev,struct net_buf * const buf)183 static void udc_event_xfer_ctrl_in(const struct device *dev, struct net_buf *const buf)
184 {
185 if (udc_ctrl_stage_is_status_in(dev) || udc_ctrl_stage_is_no_data(dev)) {
186 /* Status stage finished, notify upper layer */
187 udc_ctrl_submit_status(dev, buf);
188 }
189
190 /* Update to next stage of control transfer */
191 udc_ctrl_update_stage(dev, buf);
192
193 if (udc_ctrl_stage_is_status_out(dev)) {
194 /* IN transfer finished, perform status stage OUT and release buffer */
195 usbd_ctrl_feed_dout(dev, 0);
196 net_buf_unref(buf);
197 }
198 }
199
udc_event_status_in(const struct device * dev)200 static void udc_event_status_in(const struct device *dev)
201 {
202 struct udc_renesas_ra_data *data = udc_get_private(dev);
203 struct net_buf *buf;
204
205 buf = udc_buf_get(dev, USB_CONTROL_EP_IN);
206 if (unlikely(buf == NULL)) {
207 LOG_DBG("ep 0x%02x queue is empty", USB_CONTROL_EP_IN);
208 return;
209 }
210
211 /* Perform status stage IN */
212 R_USBD_XferStart(&data->udc, USB_CONTROL_EP_IN, NULL, 0);
213
214 udc_event_xfer_ctrl_in(dev, buf);
215 }
216
udc_event_xfer_ctrl_out(const struct device * dev,struct net_buf * const buf,uint32_t len)217 static void udc_event_xfer_ctrl_out(const struct device *dev, struct net_buf *const buf,
218 uint32_t len)
219 {
220 net_buf_add(buf, len);
221
222 if (udc_ctrl_stage_is_status_out(dev)) {
223 /* Status stage finished, notify upper layer */
224 udc_ctrl_submit_status(dev, buf);
225 }
226
227 /* Update to next stage of control transfer */
228 udc_ctrl_update_stage(dev, buf);
229
230 if (udc_ctrl_stage_is_status_in(dev)) {
231 udc_ctrl_submit_s_out_status(dev, buf);
232 }
233 }
234
udc_event_xfer_complete(const struct device * dev,struct udc_renesas_ra_evt * evt)235 static void udc_event_xfer_complete(const struct device *dev, struct udc_renesas_ra_evt *evt)
236 {
237 struct net_buf *buf;
238 struct udc_renesas_ra_data *data = udc_get_private(dev);
239
240 uint8_t ep = evt->hal_evt.xfer_complete.ep_addr;
241 usbd_xfer_result_t result = evt->hal_evt.xfer_complete.result;
242 uint32_t len = evt->hal_evt.xfer_complete.len;
243
244 udc_ep_set_busy(dev, ep, false);
245
246 buf = udc_buf_peek(dev, ep);
247 if (buf == NULL) {
248 return;
249 }
250
251 if (result != USBD_XFER_RESULT_SUCCESS) {
252 goto error;
253 }
254
255 if (USB_EP_DIR_IS_IN(ep) && udc_ep_buf_has_zlp(buf)) {
256 /* Send ZLP, notification about transfer complete should come again */
257 udc_ep_buf_clear_zlp(buf);
258 if (FSP_SUCCESS != R_USBD_XferStart(&data->udc, ep, NULL, 0)) {
259 goto error;
260 }
261
262 return;
263 }
264
265 buf = udc_buf_get(dev, ep);
266
267 if (ep == USB_CONTROL_EP_IN) {
268 udc_event_xfer_ctrl_in(dev, buf);
269 } else if (ep == USB_CONTROL_EP_OUT) {
270 udc_event_xfer_ctrl_out(dev, buf, len);
271 } else {
272 if (USB_EP_DIR_IS_OUT(ep)) {
273 net_buf_add(buf, len);
274 }
275 udc_submit_ep_event(dev, buf, 0);
276 }
277
278 return;
279 error:
280 udc_submit_ep_event(dev, buf, -EIO);
281 }
282
renesas_ra_thread_handler(void * const arg)283 static ALWAYS_INLINE void renesas_ra_thread_handler(void *const arg)
284 {
285 const struct device *dev = (const struct device *)arg;
286
287 LOG_DBG("Driver %p thread started", dev);
288 while (true) {
289 struct udc_renesas_ra_evt evt;
290
291 k_msgq_get(&drv_msgq, &evt, K_FOREVER);
292 switch (evt.type) {
293 case UDC_RENESAS_RA_EVT_HAL: {
294 switch (evt.hal_evt.event_id) {
295 case USBD_EVENT_SETUP_RECEIVED:
296 udc_event_xfer_setup(dev, &evt);
297 break;
298
299 case USBD_EVENT_XFER_COMPLETE:
300 udc_event_xfer_complete(dev, &evt);
301 break;
302
303 default:
304 break;
305 }
306 break;
307 }
308
309 case UDC_RENESAS_RA_EVT_XFER:
310 udc_event_xfer_next(dev, evt.ep);
311 break;
312
313 case UDC_RENESAS_RA_EVT_STATUS:
314 udc_event_status_in(dev);
315 break;
316
317 default:
318 break;
319 }
320 }
321 }
322
udc_renesas_ra_ep_enqueue(const struct device * dev,struct udc_ep_config * const cfg,struct net_buf * buf)323 static int udc_renesas_ra_ep_enqueue(const struct device *dev, struct udc_ep_config *const cfg,
324 struct net_buf *buf)
325 {
326 struct udc_renesas_ra_evt evt = {};
327
328 LOG_DBG("%p enqueue %p", dev, buf);
329
330 udc_buf_put(cfg, buf);
331
332 evt.ep = cfg->addr;
333 if (cfg->addr == USB_CONTROL_EP_IN && buf->len == 0) {
334 evt.type = UDC_RENESAS_RA_EVT_STATUS;
335 } else {
336 evt.type = UDC_RENESAS_RA_EVT_XFER;
337 }
338
339 k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
340
341 if (cfg->stat.halted) {
342 LOG_DBG("ep 0x%02x halted", cfg->addr);
343 }
344
345 return 0;
346 }
347
udc_renesas_ra_ep_dequeue(const struct device * dev,struct udc_ep_config * const cfg)348 static int udc_renesas_ra_ep_dequeue(const struct device *dev, struct udc_ep_config *const cfg)
349 {
350 struct udc_renesas_ra_data *data = udc_get_private(dev);
351 unsigned int lock_key;
352 struct net_buf *buf;
353
354 lock_key = irq_lock();
355
356 buf = udc_buf_get_all(dev, cfg->addr);
357 if (buf != NULL) {
358 udc_submit_ep_event(dev, buf, -ECONNABORTED);
359 }
360
361 if (FSP_SUCCESS != R_USBD_XferAbort(&data->udc, cfg->addr)) {
362 return -EIO;
363 }
364
365 udc_ep_set_busy(dev, cfg->addr, false);
366
367 irq_unlock(lock_key);
368
369 return 0;
370 }
371
udc_renesas_ra_ep_enable(const struct device * dev,struct udc_ep_config * const cfg)372 static int udc_renesas_ra_ep_enable(const struct device *dev, struct udc_ep_config *const cfg)
373 {
374 struct udc_renesas_ra_data *data = udc_get_private(dev);
375 usbd_desc_endpoint_t ep_desc;
376
377 if (USB_EP_GET_IDX(cfg->addr) == 0) {
378 return 0;
379 }
380
381 ep_desc.bLength = sizeof(struct usb_ep_descriptor);
382 ep_desc.bDescriptorType = USB_DESC_ENDPOINT;
383 ep_desc.bEndpointAddress = cfg->addr;
384 ep_desc.bmAttributes = cfg->attributes;
385 ep_desc.wMaxPacketSize = cfg->mps;
386 ep_desc.bInterval = cfg->interval;
387
388 if (FSP_SUCCESS != R_USBD_EdptOpen(&data->udc, &ep_desc)) {
389 return -EIO;
390 }
391
392 LOG_DBG("Enable ep 0x%02x", cfg->addr);
393
394 return 0;
395 }
396
udc_renesas_ra_ep_disable(const struct device * dev,struct udc_ep_config * const cfg)397 static int udc_renesas_ra_ep_disable(const struct device *dev, struct udc_ep_config *const cfg)
398 {
399 struct udc_renesas_ra_data *data = udc_get_private(dev);
400
401 if (USB_EP_GET_IDX(cfg->addr) == 0) {
402 return 0;
403 }
404
405 if (FSP_SUCCESS != R_USBD_EdptClose(&data->udc, cfg->addr)) {
406 return -EIO;
407 }
408
409 LOG_DBG("Disable ep 0x%02x", cfg->addr);
410
411 return 0;
412 }
413
udc_renesas_ra_ep_set_halt(const struct device * dev,struct udc_ep_config * const cfg)414 static int udc_renesas_ra_ep_set_halt(const struct device *dev, struct udc_ep_config *const cfg)
415 {
416 struct udc_renesas_ra_data *data = udc_get_private(dev);
417
418 LOG_DBG("Set halt ep 0x%02x", cfg->addr);
419
420 if (FSP_SUCCESS != R_USBD_EdptStall(&data->udc, cfg->addr)) {
421 return -EIO;
422 }
423
424 cfg->stat.halted = true;
425
426 return 0;
427 }
428
udc_renesas_ra_ep_clear_halt(const struct device * dev,struct udc_ep_config * const cfg)429 static int udc_renesas_ra_ep_clear_halt(const struct device *dev, struct udc_ep_config *const cfg)
430 {
431 struct udc_renesas_ra_data *data = udc_get_private(dev);
432
433 LOG_DBG("Clear halt ep 0x%02x", cfg->addr);
434
435 if (FSP_SUCCESS != R_USBD_EdptClearStall(&data->udc, cfg->addr)) {
436 return -EIO;
437 }
438
439 cfg->stat.halted = false;
440
441 return 0;
442 }
443
udc_renesas_ra_set_address(const struct device * dev,const uint8_t addr)444 static int udc_renesas_ra_set_address(const struct device *dev, const uint8_t addr)
445 {
446 /* The USB controller will automatically perform a response to the SET_ADRRESS request. */
447 LOG_DBG("Set new address %u for %p", addr, dev);
448
449 return 0;
450 }
451
udc_renesas_ra_host_wakeup(const struct device * dev)452 static int udc_renesas_ra_host_wakeup(const struct device *dev)
453 {
454 struct udc_renesas_ra_data *data = udc_get_private(dev);
455
456 if (FSP_SUCCESS != R_USBD_RemoteWakeup(&data->udc)) {
457 return -EIO;
458 }
459
460 LOG_DBG("Remote wakeup from %p", dev);
461
462 return 0;
463 }
464
udc_renesas_ra_device_speed(const struct device * dev)465 static enum udc_bus_speed udc_renesas_ra_device_speed(const struct device *dev)
466 {
467 struct udc_data *data = dev->data;
468
469 return data->caps.hs ? UDC_BUS_SPEED_HS : UDC_BUS_SPEED_FS;
470 }
471
udc_renesas_ra_enable(const struct device * dev)472 static int udc_renesas_ra_enable(const struct device *dev)
473 {
474 struct udc_renesas_ra_data *data = udc_get_private(dev);
475
476 if (FSP_SUCCESS != R_USBD_Connect(&data->udc)) {
477 return -EIO;
478 }
479
480 LOG_DBG("Enable device %p", dev);
481
482 return 0;
483 }
484
udc_renesas_ra_disable(const struct device * dev)485 static int udc_renesas_ra_disable(const struct device *dev)
486 {
487 struct udc_renesas_ra_data *data = udc_get_private(dev);
488
489 if (FSP_SUCCESS != R_USBD_Disconnect(&data->udc)) {
490 return -EIO;
491 }
492
493 LOG_DBG("Disable device %p", dev);
494
495 return 0;
496 }
497
udc_renesas_ra_init(const struct device * dev)498 static int udc_renesas_ra_init(const struct device *dev)
499 {
500 struct udc_renesas_ra_data *data = udc_get_private(dev);
501
502 if (FSP_SUCCESS != R_USBD_Open(&data->udc, &data->udc_cfg)) {
503 return -EIO;
504 }
505
506 if (udc_ep_enable_internal(dev, USB_CONTROL_EP_OUT, USB_EP_TYPE_CONTROL, 64, 0)) {
507 LOG_ERR("Failed to enable control endpoint");
508 return -EIO;
509 }
510
511 if (udc_ep_enable_internal(dev, USB_CONTROL_EP_IN, USB_EP_TYPE_CONTROL, 64, 0)) {
512 LOG_ERR("Failed to enable control endpoint");
513 return -EIO;
514 }
515
516 #if DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_usbhs)
517 if (data->udc_cfg.hs_irq != (IRQn_Type)BSP_IRQ_DISABLED) {
518 irq_enable(data->udc_cfg.hs_irq);
519 }
520 #endif
521
522 if (data->udc_cfg.irq != (IRQn_Type)BSP_IRQ_DISABLED) {
523 irq_enable(data->udc_cfg.irq);
524 }
525
526 if (data->udc_cfg.irq_r != (IRQn_Type)BSP_IRQ_DISABLED) {
527 irq_enable(data->udc_cfg.irq_r);
528 }
529
530 return 0;
531 }
532
udc_renesas_ra_shutdown(const struct device * dev)533 static int udc_renesas_ra_shutdown(const struct device *dev)
534 {
535 struct udc_renesas_ra_data *data = udc_get_private(dev);
536
537 if (udc_ep_disable_internal(dev, USB_CONTROL_EP_OUT)) {
538 LOG_ERR("Failed to disable control endpoint");
539 return -EIO;
540 }
541
542 if (udc_ep_disable_internal(dev, USB_CONTROL_EP_IN)) {
543 LOG_ERR("Failed to disable control endpoint");
544 return -EIO;
545 }
546
547 if (FSP_SUCCESS != R_USBD_Close(&data->udc)) {
548 return -EIO;
549 }
550
551 return 0;
552 }
553
udc_renesas_ra_clock_check(const struct device * dev)554 static int udc_renesas_ra_clock_check(const struct device *dev)
555 {
556 const struct udc_renesas_ra_config *config = dev->config;
557
558 #if USBHS_PHY_CLOCK_SOURCE_IS_XTAL
559 if (config->speed_idx == UDC_BUS_SPEED_HS) {
560 if (BSP_CFG_XTAL_HZ == 0) {
561 LOG_ERR("XTAL clock should be provided");
562 return -EINVAL;
563 }
564
565 return 0;
566 }
567 #endif
568
569 for (size_t i = 0; i < config->num_of_clocks; i++) {
570 const struct device *clock_dev = *(config->clocks + i);
571 const struct clock_control_ra_pclk_cfg *clock_cfg = clock_dev->config;
572 uint32_t clk_src_rate;
573 uint32_t clock_rate;
574
575 if (!device_is_ready(clock_dev)) {
576 LOG_ERR("%s is not ready", clock_dev->name);
577 return -ENODEV;
578 }
579
580 clk_src_rate = R_BSP_SourceClockHzGet(clock_cfg->clk_src);
581 clock_rate = clk_src_rate / clock_cfg->clk_div;
582
583 if (strcmp(clock_dev->name, "uclk") == 0 && clock_rate != MHZ(48)) {
584 LOG_ERR("Setting for uclk should be 48Mhz");
585 return -ENOTSUP;
586 }
587
588 #if DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_usbhs)
589 if (strcmp(clock_dev->name, "u60clk") == 0 && clock_rate != MHZ(60)) {
590 LOG_ERR("Setting for u60clk should be 60Mhz");
591 return -ENOTSUP;
592 }
593 #endif
594 }
595
596 return 0;
597 }
598
udc_renesas_ra_driver_preinit(const struct device * dev)599 static int udc_renesas_ra_driver_preinit(const struct device *dev)
600 {
601 const struct udc_renesas_ra_config *config = dev->config;
602 struct udc_renesas_ra_data *priv = udc_get_private(dev);
603 struct udc_data *data = dev->data;
604 uint16_t mps = 1023;
605 int err;
606
607 #if !USBHS_PHY_CLOCK_SOURCE_IS_XTAL
608 if (priv->udc_cfg.usb_speed == USBD_SPEED_HS) {
609 LOG_ERR("High-speed operation is not supported in case PHY clock source is not "
610 "XTAL");
611 return -ENOTSUP;
612 }
613 #endif
614
615 if (config->speed_idx == UDC_BUS_SPEED_HS) {
616 if (!(priv->udc_cfg.usb_speed == USBD_SPEED_HS ||
617 priv->udc_cfg.usb_speed == USBD_SPEED_FS)) {
618 LOG_ERR("USBHS module only support high-speed and full-speed device");
619 return -ENOTSUP;
620 }
621 } else {
622 /* config->speed_idx == UDC_BUS_SPEED_FS */
623 if (priv->udc_cfg.usb_speed != USBD_SPEED_FS) {
624 LOG_ERR("USBFS module only support full-speed device");
625 return -ENOTSUP;
626 }
627 }
628
629 err = udc_renesas_ra_clock_check(dev);
630 if (err < 0) {
631 return err;
632 }
633
634 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
635 if (err < 0) {
636 return err;
637 }
638
639 k_mutex_init(&data->mutex);
640
641 data->caps.rwup = true;
642 data->caps.mps0 = UDC_MPS0_64;
643 if (priv->udc_cfg.usb_speed == USBD_SPEED_HS) {
644 data->caps.hs = true;
645 mps = 1024;
646 }
647
648 for (int i = 0; i < config->num_of_eps; i++) {
649 config->ep_cfg_out[i].caps.out = 1;
650 if (i == 0) {
651 config->ep_cfg_out[i].caps.control = 1;
652 config->ep_cfg_out[i].caps.mps = 64;
653 } else {
654 config->ep_cfg_out[i].caps.bulk = 1;
655 config->ep_cfg_out[i].caps.interrupt = 1;
656 config->ep_cfg_out[i].caps.iso = 1;
657 config->ep_cfg_out[i].caps.mps = mps;
658 }
659
660 config->ep_cfg_out[i].addr = USB_EP_DIR_OUT | i;
661 err = udc_register_ep(dev, &config->ep_cfg_out[i]);
662 if (err != 0) {
663 LOG_ERR("Failed to register endpoint");
664 return err;
665 }
666 }
667
668 for (int i = 0; i < config->num_of_eps; i++) {
669 config->ep_cfg_in[i].caps.in = 1;
670 if (i == 0) {
671 config->ep_cfg_in[i].caps.control = 1;
672 config->ep_cfg_in[i].caps.mps = 64;
673 } else {
674 config->ep_cfg_in[i].caps.bulk = 1;
675 config->ep_cfg_in[i].caps.interrupt = 1;
676 config->ep_cfg_in[i].caps.iso = 1;
677 config->ep_cfg_in[i].caps.mps = mps;
678 }
679
680 config->ep_cfg_in[i].addr = USB_EP_DIR_IN | i;
681 err = udc_register_ep(dev, &config->ep_cfg_in[i]);
682 if (err != 0) {
683 LOG_ERR("Failed to register endpoint");
684 return err;
685 }
686 }
687
688 #if DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_usbhs)
689 if (priv->udc_cfg.hs_irq != (IRQn_Type)BSP_IRQ_DISABLED) {
690 R_ICU->IELSR[priv->udc_cfg.hs_irq] = BSP_PRV_IELS_ENUM(EVENT_USBHS_USB_INT_RESUME);
691 }
692 #endif
693
694 if (priv->udc_cfg.irq != (IRQn_Type)BSP_IRQ_DISABLED) {
695 R_ICU->IELSR[priv->udc_cfg.irq] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT);
696 }
697
698 if (priv->udc_cfg.irq_r != (IRQn_Type)BSP_IRQ_DISABLED) {
699 R_ICU->IELSR[priv->udc_cfg.irq_r] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME);
700 }
701
702 config->make_thread(dev);
703 LOG_INF("Device %p (max. speed %d)", dev, priv->udc_cfg.usb_speed);
704
705 return 0;
706 }
707
udc_renesas_ra_lock(const struct device * dev)708 static void udc_renesas_ra_lock(const struct device *dev)
709 {
710 udc_lock_internal(dev, K_FOREVER);
711 }
712
udc_renesas_ra_unlock(const struct device * dev)713 static void udc_renesas_ra_unlock(const struct device *dev)
714 {
715 udc_unlock_internal(dev);
716 }
717
718 static const struct udc_api udc_renesas_ra_api = {
719 .lock = udc_renesas_ra_lock,
720 .unlock = udc_renesas_ra_unlock,
721 .device_speed = udc_renesas_ra_device_speed,
722 .init = udc_renesas_ra_init,
723 .enable = udc_renesas_ra_enable,
724 .disable = udc_renesas_ra_disable,
725 .shutdown = udc_renesas_ra_shutdown,
726 .set_address = udc_renesas_ra_set_address,
727 .host_wakeup = udc_renesas_ra_host_wakeup,
728 .ep_enable = udc_renesas_ra_ep_enable,
729 .ep_disable = udc_renesas_ra_ep_disable,
730 .ep_set_halt = udc_renesas_ra_ep_set_halt,
731 .ep_clear_halt = udc_renesas_ra_ep_clear_halt,
732 .ep_enqueue = udc_renesas_ra_ep_enqueue,
733 .ep_dequeue = udc_renesas_ra_ep_dequeue,
734 };
735
736 #define DT_DRV_COMPAT renesas_ra_udc
737
738 #define USB_RENESAS_RA_MODULE_NUMBER(id) (DT_REG_ADDR(id) == R_USB_FS0_BASE ? 0 : 1)
739
740 #define USB_RENESAS_RA_IRQ_GET(id, name, cell) \
741 COND_CODE_1(DT_IRQ_HAS_NAME(id, name), (DT_IRQ_BY_NAME(id, name, cell)), \
742 ((IRQn_Type) BSP_IRQ_DISABLED))
743
744 #define USB_RENESAS_RA_MAX_SPEED_IDX(id) \
745 (DT_NODE_HAS_COMPAT(id, renesas_ra_usbhs) ? UDC_BUS_SPEED_HS : UDC_BUS_SPEED_FS)
746
747 #define USB_RENESAS_RA_SPEED_IDX(id) \
748 (DT_NODE_HAS_COMPAT(id, renesas_ra_usbhs) \
749 ? DT_ENUM_IDX_OR(id, maximum_speed, UDC_BUS_SPEED_HS) \
750 : DT_ENUM_IDX_OR(id, maximum_speed, UDC_BUS_SPEED_FS))
751
752 #define USB_RENESAS_RA_IRQ_CONNECT(idx, n) \
753 IRQ_CONNECT(DT_IRQ_BY_IDX(DT_INST_PARENT(n), idx, irq), \
754 DT_IRQ_BY_IDX(DT_INST_PARENT(n), idx, priority), \
755 udc_renesas_ra_interrupt_handler, DEVICE_DT_INST_GET(n), 0)
756
757 #define USB_RENESAS_RA_CLOCKS_GET(idx, id) \
758 DEVICE_DT_GET_OR_NULL(DT_PHANDLE_BY_IDX(id, phys_clock, idx))
759
760 #define UDC_RENESAS_RA_DEVICE_DEFINE(n) \
761 PINCTRL_DT_DEFINE(DT_INST_PARENT(n)); \
762 K_THREAD_STACK_DEFINE(udc_renesas_ra_stack_##n, CONFIG_UDC_RENESAS_RA_STACK_SIZE); \
763 \
764 static const struct device *udc_renesas_ra_clock_dev_##n[] = { \
765 LISTIFY(DT_PROP_LEN_OR(DT_INST_PARENT(n), phys_clock, 0), \
766 USB_RENESAS_RA_CLOCKS_GET, (,), DT_INST_PARENT(n)) \
767 }; \
768 \
769 static void udc_renesas_ra_thread_##n(void *dev, void *arg1, void *arg2) \
770 { \
771 renesas_ra_thread_handler(dev); \
772 } \
773 \
774 static void udc_renesas_ra_make_thread_##n(const struct device *dev) \
775 { \
776 struct udc_renesas_ra_data *priv = udc_get_private(dev); \
777 \
778 k_thread_create(&priv->thread_data, udc_renesas_ra_stack_##n, \
779 K_THREAD_STACK_SIZEOF(udc_renesas_ra_stack_##n), \
780 udc_renesas_ra_thread_##n, (void *)dev, NULL, NULL, \
781 K_PRIO_COOP(CONFIG_UDC_RENESAS_RA_THREAD_PRIORITY), K_ESSENTIAL, \
782 K_NO_WAIT); \
783 k_thread_name_set(&priv->thread_data, dev->name); \
784 } \
785 \
786 static struct udc_ep_config ep_cfg_in##n[DT_PROP(DT_INST_PARENT(n), num_bidir_endpoints)]; \
787 static struct udc_ep_config \
788 ep_cfg_out##n[DT_PROP(DT_INST_PARENT(n), num_bidir_endpoints)]; \
789 \
790 static const struct udc_renesas_ra_config udc_renesas_ra_config_##n = { \
791 .pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(n)), \
792 .clocks = udc_renesas_ra_clock_dev_##n, \
793 .num_of_clocks = DT_PROP_LEN_OR(DT_INST_PARENT(n), phys_clock, 0), \
794 .num_of_eps = DT_PROP(DT_INST_PARENT(n), num_bidir_endpoints), \
795 .ep_cfg_in = ep_cfg_in##n, \
796 .ep_cfg_out = ep_cfg_out##n, \
797 .make_thread = udc_renesas_ra_make_thread_##n, \
798 .speed_idx = USB_RENESAS_RA_MAX_SPEED_IDX(DT_INST_PARENT(n)), \
799 }; \
800 \
801 static struct udc_renesas_ra_data udc_priv_##n = { \
802 .udc_cfg = { \
803 .module_number = USB_RENESAS_RA_MODULE_NUMBER(DT_INST_PARENT(n)), \
804 .usb_speed = USB_RENESAS_RA_SPEED_IDX(DT_INST_PARENT(n)), \
805 .irq = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbfs_i, irq), \
806 .irq_r = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbfs_r, irq), \
807 .hs_irq = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbhs_ir, irq), \
808 .ipl = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbfs_i, priority), \
809 .ipl_r = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbfs_r, priority), \
810 .hsipl = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbhs_ir, priority), \
811 .p_context = DEVICE_DT_INST_GET(n), \
812 .p_callback = udc_renesas_ra_event_handler, \
813 }, \
814 }; \
815 \
816 static struct udc_data udc_data_##n = { \
817 .mutex = Z_MUTEX_INITIALIZER(udc_data_##n.mutex), \
818 .priv = &udc_priv_##n, \
819 }; \
820 \
821 int udc_renesas_ra_driver_preinit##n(const struct device *dev) \
822 { \
823 LISTIFY(DT_NUM_IRQS(DT_INST_PARENT(n)), USB_RENESAS_RA_IRQ_CONNECT, (;), n); \
824 return udc_renesas_ra_driver_preinit(dev); \
825 } \
826 \
827 DEVICE_DT_INST_DEFINE(n, udc_renesas_ra_driver_preinit##n, NULL, &udc_data_##n, \
828 &udc_renesas_ra_config_##n, POST_KERNEL, \
829 CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &udc_renesas_ra_api);
830
831 DT_INST_FOREACH_STATUS_OKAY(UDC_RENESAS_RA_DEVICE_DEFINE)
832
