1/*
2 * Copyright (c) 2024 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv6-m.dtsi>
8#include <zephyr/dt-bindings/i2c/i2c.h>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/pwm/pwm.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
13#include <zephyr/dt-bindings/reset/stm32wb0_reset.h>
14#include <zephyr/dt-bindings/dma/stm32_dma.h>
15#include <freq.h>
16#include <mem.h>
17
18/* NOTE: for some registers, the reserved size in the memory map differs
19 * between WB05/09 and WB06/07. In these cases, if all the registers fit
20 * in the smallest size, the peripheral is defined in this file with the
21 * smallest size in the 'reg' property.
22 */
23/ {
24	chosen {
25		zephyr,flash-controller = &flash;
26		zephyr,bt-hci = &bt_hci_wb0;
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		cpu0: cpu@0 {
34			device_type = "cpu";
35			compatible = "arm,cortex-m0+";
36			reg = <0>;
37		};
38	};
39
40	sram0: memory@20000000 {
41		compatible = "mmio-sram";
42	};
43
44	clocks {
45		/* High-speed clock nodes
46		 * These nodes must only be used as input to
47		 * the RCC node (i.e., 'clocks' property)
48		 */
49		clk_hse: clk-hse {
50			#clock-cells = <0>;
51			compatible = "fixed-clock";
52			clock-frequency = <DT_FREQ_M(32)>;
53			status = "disabled";
54		};
55
56		clk_hsi: clk-hsi {
57			#clock-cells = <0>;
58			compatible = "fixed-clock";
59			clock-frequency = <DT_FREQ_M(64)>;
60			status = "disabled";
61		};
62
63		/* Dummy node representing the RC64MPLL block in PLL mode
64		 * Using this node as RCC node input requires HSE to be enabled.
65		 */
66		pll: pll64m {
67			#clock-cells = <0>;
68			compatible = "fixed-clock";
69			clock-frequency = <DT_FREQ_M(64)>;
70			status = "disabled";
71		};
72
73		/* Slow speed clock nodes
74		 * These nodes must only be used for the
75		 * 'slow-clock' property of the RCC node.
76		 */
77		clk_lse: clk-lse {
78			#clock-cells = <0>;
79			compatible = "st,stm32-lse-clock";
80			clock-frequency = <32768>;
81			driving-capability = <1>;
82			status = "disabled";
83		};
84
85		clk_lsi: clk-lsi {
86			/* "fixed-clock" compatible is required for compatibility with the
87			 * macros in `include/drivers/clock_control/stm32_clock_control.h`
88			 */
89			#clock-cells = <0>;
90			compatible = "st,stm32wb0-lsi-clock", "fixed-clock";
91			clock-frequency = <DT_FREQ_K(32)>;
92			status = "disabled";
93		};
94
95		/* Dummy node representing the "CLK_16MHz/512" slow clock source.
96		 * WARNING: this clock is not active in DEEPSTOP, so all slow clock peripherals
97		 * are stopped, and cannot wake up the SoC, if this is selected as slow-clock!
98		 */
99		clk_16mhz_div512: clk-16mhz-div512 {
100			#clock-cells = <0>;
101			compatible = "fixed-clock";
102			clock-frequency = <(DT_FREQ_M(16) / 512)>;
103			status = "disabled";
104		};
105	};
106
107	soc {
108		flash: flash-controller@40001000 {
109			compatible = "st,stm32wb0-flash-controller", "st,stm32-flash-controller";
110			reg = <0x40001000 DT_SIZE_K(1)>;
111			interrupts = <0 0>;
112
113			#address-cells = <1>;
114			#size-cells = <1>;
115
116			flash0: flash@10040000 {
117				compatible = "st,stm32-nv-flash", "soc-nv-flash";
118				write-block-size = <4>;
119				erase-block-size = <2048>;
120				/* maximum erase time(ms) for a page (2K) */
121				max-erase-time = <40>;
122			};
123		};
124
125		rcc: rcc@48400000 {
126			compatible = "st,stm32wb0-rcc";
127			reg = <0x48400000 DT_SIZE_K(1)>;
128			#clock-cells = <2>;
129
130			rctl: reset-controller {
131				compatible = "st,stm32-rcc-rctl";
132				#reset-cells = <1>;
133			};
134		};
135
136		pwrc: power@48500000 {
137			compatible = "st,stm32wb0-pwr";
138			reg = <0x48500000 DT_SIZE_K(1)>;
139		};
140
141		/* STM32WB0 GPIO interrupt controller
142		 *
143		 * The 'reg' property corresponds to the SYSCFG memory range,
144		 * because that's where the GPIO INTC registers are located.
145		 */
146		gpio_intc: interrupt-controller@40000000 {
147			compatible = "st,stm32wb0-gpio-intc";
148			interrupt-controller;
149			#interrupt-cells = <1>;
150			#address-cells = <1>;
151			reg = <0x40000000 64>;
152			num-lines = <32>;
153			interrupts = <15 0>, <16 0>;
154			interrupt-names = "gpioa", "gpiob";
155			line-ranges = <0 16>, <16 16>;
156		};
157
158		pinctrl: pin-controller@48000000 {
159			compatible = "st,stm32-pinctrl";
160			#address-cells = <1>;
161			#size-cells = <1>;
162			reg = <0x48000000 DT_SIZE_M(2)>;
163
164			gpioa: gpio@48000000 {
165				compatible = "st,stm32-gpio";
166				gpio-controller;
167				#gpio-cells = <2>;
168				reg = <0x48000000 DT_SIZE_K(1)>;
169				clocks = <&rcc STM32_CLOCK(AHB0, 2)>;
170			};
171
172			gpiob: gpio@48100000 {
173				compatible = "st,stm32-gpio";
174				gpio-controller;
175				#gpio-cells = <2>;
176				reg = <0x48100000 DT_SIZE_K(1)>;
177				clocks = <&rcc STM32_CLOCK(AHB0, 3)>;
178			};
179		};
180
181		usart1: serial@41004000 {
182			compatible = "st,stm32-usart", "st,stm32-uart";
183			reg = <0x41004000 DT_SIZE_K(1)>;
184
185			clocks = <&rcc STM32_CLOCK(APB1, 10)>;
186			resets = <&rctl STM32_RESET(APB1, 10)>;
187			interrupts = <8 0>;
188			status = "disabled";
189		};
190
191		lpuart1: serial@41005000 {
192			compatible = "st,stm32-lpuart", "st,stm32-uart";
193			reg = <0x41005000 DT_SIZE_K(1)>;
194			clocks = <&rcc STM32_CLOCK(APB1, 8)>;
195			resets = <&rctl STM32_RESET(APB1, 8)>;
196			interrupts = <9 0>;
197			status = "disabled";
198		};
199
200		i2c1: i2c@41000000 {
201			compatible = "st,stm32-i2c-v2";
202			clock-frequency = <I2C_BITRATE_STANDARD>;
203			#address-cells = <1>;
204			#size-cells = <0>;
205			reg = <0x41000000 DT_SIZE_K(1)>;
206			clocks = <&rcc STM32_CLOCK(APB1, 21)>;
207			interrupts = <3 0>;
208			interrupt-names = "combined";
209			status = "disabled";
210		};
211
212		spi3: spi@41007000 {
213			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
214			#address-cells = <1>;
215			#size-cells = <0>;
216			reg = <0x41007000 DT_SIZE_K(1)>;
217			clocks = <&rcc STM32_CLOCK(APB1, 14)>;
218			interrupts = <7 0>;
219			status = "disabled";
220		};
221
222		adc1: adc@41006000 {
223			compatible = "st,stm32wb0-adc";
224			reg = <0x41006000 256>;
225			/* On STM32WB0, the two ADC clock domains (ANALOG / DIGITAL)
226			 * can be controlled independently. Expose this feature to
227			 * the driver by having two `clocks` property entries:
228			 *  - first entry is digital part of ADC block (always-on)
229			 *  - second entry is analog part of ADC block (on-demand)
230			 */
231			clocks = <&rcc STM32_CLOCK(APB1, 4)>,
232				 <&rcc STM32_CLOCK(APB1, 5)>;
233			interrupts = <12 0>;
234			#io-channel-cells = <1>;
235			status = "disabled";
236		};
237
238		dma1: dma@48700000 {
239			compatible = "st,stm32-dma-v2bis";
240			#dma-cells = <2>;
241			reg = <0x48700000 256>;
242			clocks = <&rcc STM32_CLOCK(AHB0, 0)>;
243			interrupts = <17 0 17 0 17 0 17 0 17 0 17 0 17 0 17 0>;
244			dma-requests = <8>;
245			dma-offset = <0>;
246			status = "disabled";
247		};
248
249		dmamux1: dmamux@48800000 {
250			compatible = "st,stm32-dmamux";
251			reg = <0x48800000 DT_SIZE_K(1)>;
252			/* `clocks` property is identical between DMA and DMAMUX
253			 * because they share a single common bit in RCC registers
254			 */
255			clocks = <&rcc STM32_CLOCK(AHB0, 0)>;
256			#dma-cells = <3>;
257			dma-channels = <8>;
258			dma-generators = <1>;
259			dma-requests= <25>;
260			status = "disabled";
261		};
262	};
263
264	bt_hci_wb0: bt_hci_wb0 {
265		compatible = "st,hci-stm32wb0";
266		status = "disabled";
267	};
268};
269
270&nvic {
271	arm,num-irq-priority-bits = <2>;
272};
273