1/* 2 * Copyright (c) 2023 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <mem.h> 9#include <zephyr/dt-bindings/pinctrl/numaker-m46x-pinctrl.h> 10#include <zephyr/dt-bindings/clock/numaker_m46x_clock.h> 11#include <zephyr/dt-bindings/reset/numaker_m46x_reset.h> 12#include <zephyr/dt-bindings/gpio/gpio.h> 13#include <zephyr/dt-bindings/i2c/i2c.h> 14#include <zephyr/dt-bindings/adc/adc.h> 15 16/ { 17 chosen { 18 zephyr,flash-controller = &fmc; 19 }; 20 21 aliases { 22 rtc = &rtc; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-m4f"; 32 reg = <0>; 33 }; 34 }; 35 36 sram0: memory@20000000 { 37 compatible = "mmio-sram"; 38 reg = <0x20000000 DT_SIZE_K(512)>; 39 }; 40 41 sysclk: system-clock { 42 compatible = "fixed-clock"; 43 clock-frequency = <200000000>; 44 #clock-cells = <0>; 45 }; 46 47 soc { 48 scc: system-clock-controller@40000200 { 49 compatible = "nuvoton,numaker-scc"; 50 reg = <0x40000200 0x100>; 51 #clock-cells = <0>; 52 /* hxt = "enable"; */ 53 lxt = "enable"; 54 hirc48m = "enable"; 55 clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 | 56 NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>; 57 core-clock = <200000000>; 58 powerdown-mode = <NUMAKER_CLK_PMUCTL_PDMSEL_DPD>; 59 60 pcc: peripheral-clock-controller { 61 compatible = "nuvoton,numaker-pcc"; 62 #clock-cells = <3>; 63 }; 64 }; 65 66 rst: reset-controller@40000000 { 67 compatible = "nuvoton,numaker-rst"; 68 reg = <0x40000000 0x20>; 69 #reset-cells = <1>; 70 status = "okay"; 71 }; 72 73 fmc: flash-controller@4000c000 { 74 compatible = "nuvoton,numaker-fmc"; 75 reg = <0x4000c000 0x110>; 76 #address-cells = <1>; 77 #size-cells = <1>; 78 79 flash0: flash@0 { 80 compatible = "soc-nv-flash"; 81 reg = <0 DT_SIZE_K(1024)>; 82 erase-block-size = <4096>; 83 write-block-size = <4>; 84 }; 85 }; 86 87 uart0: serial@40070000 { 88 compatible = "nuvoton,numaker-uart"; 89 reg = <0x40070000 0x1000>; 90 interrupts = <36 0>; 91 resets = <&rst NUMAKER_UART0_RST>; 92 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC 93 NUMAKER_CLK_CLKDIV0_UART0(1)>; 94 status = "disabled"; 95 }; 96 97 uart1: serial@40071000 { 98 compatible = "nuvoton,numaker-uart"; 99 reg = <0x40071000 0x1000>; 100 interrupts = <37 0>; 101 resets = <&rst NUMAKER_UART1_RST>; 102 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC 103 NUMAKER_CLK_CLKDIV0_UART1(1)>; 104 status = "disabled"; 105 }; 106 107 uart2: serial@40072000 { 108 compatible = "nuvoton,numaker-uart"; 109 reg = <0x40072000 0x1000>; 110 interrupts = <48 0>; 111 resets = <&rst NUMAKER_UART2_RST>; 112 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC 113 NUMAKER_CLK_CLKDIV4_UART2(1)>; 114 status = "disabled"; 115 }; 116 117 uart3: serial@40073000 { 118 compatible = "nuvoton,numaker-uart"; 119 reg = <0x40073000 0x1000>; 120 interrupts = <49 0>; 121 resets = <&rst NUMAKER_UART3_RST>; 122 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC 123 NUMAKER_CLK_CLKDIV4_UART3(1)>; 124 status = "disabled"; 125 }; 126 127 uart4: serial@40074000 { 128 compatible = "nuvoton,numaker-uart"; 129 reg = <0x40074000 0x1000>; 130 interrupts = <74 0>; 131 resets = <&rst NUMAKER_UART4_RST>; 132 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC 133 NUMAKER_CLK_CLKDIV4_UART4(1)>; 134 status = "disabled"; 135 }; 136 137 uart5: serial@40075000 { 138 compatible = "nuvoton,numaker-uart"; 139 reg = <0x40075000 0x1000>; 140 interrupts = <75 0>; 141 resets = <&rst NUMAKER_UART5_RST>; 142 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC 143 NUMAKER_CLK_CLKDIV4_UART5(1)>; 144 status = "disabled"; 145 }; 146 147 uart6: serial@40076000 { 148 compatible = "nuvoton,numaker-uart"; 149 reg = <0x40076000 0x1000>; 150 interrupts = <102 0>; 151 resets = <&rst NUMAKER_UART6_RST>; 152 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC 153 NUMAKER_CLK_CLKDIV4_UART6(1)>; 154 status = "disabled"; 155 }; 156 157 uart7: serial@40077000 { 158 compatible = "nuvoton,numaker-uart"; 159 reg = <0x40077000 0x1000>; 160 interrupts = <103 0>; 161 resets = <&rst NUMAKER_UART7_RST>; 162 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC 163 NUMAKER_CLK_CLKDIV4_UART7(1)>; 164 status = "disabled"; 165 }; 166 167 uart8: serial@40078000 { 168 compatible = "nuvoton,numaker-uart"; 169 reg = <0x40078000 0x1000>; 170 interrupts = <99 0>; 171 resets = <&rst NUMAKER_UART8_RST>; 172 clocks = <&pcc NUMAKER_UART8_MODULE NUMAKER_CLK_CLKSEL2_UART8SEL_HIRC 173 NUMAKER_CLK_CLKDIV5_UART8(1)>; 174 status = "disabled"; 175 }; 176 177 uart9: serial@40079000 { 178 compatible = "nuvoton,numaker-uart"; 179 reg = <0x40079000 0x1000>; 180 interrupts = <100 0>; 181 resets = <&rst NUMAKER_UART9_RST>; 182 clocks = <&pcc NUMAKER_UART9_MODULE NUMAKER_CLK_CLKSEL2_UART9SEL_HIRC 183 NUMAKER_CLK_CLKDIV5_UART9(1)>; 184 status = "disabled"; 185 }; 186 187 pinctrl: pin-controller@40000080 { 188 compatible = "nuvoton,numaker-pinctrl"; 189 reg = <0x40000080 0x28 190 0x40000500 0xa0>; 191 reg-names = "mfos", "mfp"; 192 status = "okay"; 193 }; 194 195 gpioa: gpio@40004000 { 196 compatible = "nuvoton,numaker-gpio"; 197 gpio-controller; 198 #gpio-cells = <2>; 199 reg = <0x40004000 0x40>; 200 clocks = <&pcc NUMAKER_GPA_MODULE 0 0>; 201 status = "disabled"; 202 interrupts = <16 2>; 203 }; 204 205 gpiob: gpio@40004040 { 206 compatible = "nuvoton,numaker-gpio"; 207 gpio-controller; 208 #gpio-cells = <2>; 209 reg = <0x40004040 0x40>; 210 clocks = <&pcc NUMAKER_GPB_MODULE 0 0>; 211 status = "disabled"; 212 interrupts = <17 2>; 213 }; 214 215 gpioc: gpio@40004080 { 216 compatible = "nuvoton,numaker-gpio"; 217 gpio-controller; 218 #gpio-cells = <2>; 219 reg = <0x40004080 0x40>; 220 clocks = <&pcc NUMAKER_GPC_MODULE 0 0>; 221 status = "disabled"; 222 interrupts = <18 2>; 223 }; 224 225 gpiod: gpio@400040c0 { 226 compatible = "nuvoton,numaker-gpio"; 227 gpio-controller; 228 #gpio-cells = <2>; 229 reg = <0x400040c0 0x40>; 230 clocks = <&pcc NUMAKER_GPD_MODULE 0 0>; 231 status = "disabled"; 232 interrupts = <19 2>; 233 }; 234 235 gpioe: gpio@40004100 { 236 compatible = "nuvoton,numaker-gpio"; 237 gpio-controller; 238 #gpio-cells = <2>; 239 reg = <0x40004100 0x40>; 240 clocks = <&pcc NUMAKER_GPE_MODULE 0 0>; 241 status = "disabled"; 242 interrupts = <20 2>; 243 }; 244 245 gpiof: gpio@40004140 { 246 compatible = "nuvoton,numaker-gpio"; 247 gpio-controller; 248 #gpio-cells = <2>; 249 reg = <0x40004140 0x40>; 250 clocks = <&pcc NUMAKER_GPF_MODULE 0 0>; 251 status = "disabled"; 252 interrupts = <21 2>; 253 }; 254 255 gpiog: gpio@40004180 { 256 compatible = "nuvoton,numaker-gpio"; 257 gpio-controller; 258 #gpio-cells = <2>; 259 reg = <0x40004180 0x40>; 260 clocks = <&pcc NUMAKER_GPG_MODULE 0 0>; 261 status = "disabled"; 262 interrupts = <72 2>; 263 }; 264 265 gpioh: gpio@400041c0 { 266 compatible = "nuvoton,numaker-gpio"; 267 gpio-controller; 268 #gpio-cells = <2>; 269 reg = <0x400041c0 0x40>; 270 clocks = <&pcc NUMAKER_GPH_MODULE 0 0>; 271 status = "disabled"; 272 interrupts = <88 2>; 273 }; 274 275 gpioi: gpio@40004200 { 276 compatible = "nuvoton,numaker-gpio"; 277 gpio-controller; 278 #gpio-cells = <2>; 279 reg = <0x40004200 0x40>; 280 clocks = <&pcc NUMAKER_GPI_MODULE 0 0>; 281 status = "disabled"; 282 interrupts = <110 2>; 283 }; 284 285 gpioj: gpio@40004240 { 286 compatible = "nuvoton,numaker-gpio"; 287 gpio-controller; 288 #gpio-cells = <2>; 289 reg = <0x40004240 0x40>; 290 clocks = <&pcc NUMAKER_GPJ_MODULE 0 0>; 291 status = "disabled"; 292 interrupts = <61 2>; 293 }; 294 295 spi0: spi@40061000 { 296 compatible = "nuvoton,numaker-spi"; 297 reg = <0x40061000 0x6c>; 298 interrupts = <23 0>; 299 resets = <&rst NUMAKER_SPI0_RST>; 300 clocks = <&pcc NUMAKER_SPI0_MODULE NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC 0>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 status = "disabled"; 304 }; 305 306 spi1: spi@40062000 { 307 compatible = "nuvoton,numaker-spi"; 308 reg = <0x40062000 0x6c>; 309 interrupts = <51 0>; 310 resets = <&rst NUMAKER_SPI1_RST>; 311 clocks = <&pcc NUMAKER_SPI1_MODULE NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC 0>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 status = "disabled"; 315 }; 316 317 spi2: spi@40063000 { 318 compatible = "nuvoton,numaker-spi"; 319 reg = <0x40063000 0x6c>; 320 interrupts = <52 0>; 321 resets = <&rst NUMAKER_SPI2_RST>; 322 clocks = <&pcc NUMAKER_SPI2_MODULE NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC 0>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 status = "disabled"; 326 }; 327 328 spi3: spi@40064000 { 329 compatible = "nuvoton,numaker-spi"; 330 reg = <0x40064000 0x6c>; 331 interrupts = <62 0>; 332 resets = <&rst NUMAKER_SPI3_RST>; 333 clocks = <&pcc NUMAKER_SPI3_MODULE NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC 0>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 status = "disabled"; 337 }; 338 339 spi4: spi@40065000 { 340 compatible = "nuvoton,numaker-spi"; 341 reg = <0x40065000 0x6c>; 342 interrupts = <63 0>; 343 resets = <&rst NUMAKER_SPI4_RST>; 344 clocks = <&pcc NUMAKER_SPI4_MODULE NUMAKER_CLK_CLKSEL4_SPI4SEL_HIRC 0>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 status = "disabled"; 348 }; 349 350 spi5: spi@40066000 { 351 compatible = "nuvoton,numaker-spi"; 352 reg = <0x40066000 0x6c>; 353 interrupts = <57 0>; 354 resets = <&rst NUMAKER_SPI5_RST>; 355 clocks = <&pcc NUMAKER_SPI5_MODULE NUMAKER_CLK_CLKSEL4_SPI5SEL_HIRC 0>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 status = "disabled"; 359 }; 360 361 spi6: spi@40067000 { 362 compatible = "nuvoton,numaker-spi"; 363 reg = <0x40067000 0x6c>; 364 interrupts = <70 0>; 365 resets = <&rst NUMAKER_SPI6_RST>; 366 clocks = <&pcc NUMAKER_SPI6_MODULE NUMAKER_CLK_CLKSEL4_SPI6SEL_HIRC 0>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 status = "disabled"; 370 }; 371 372 spi7: spi@40068000 { 373 compatible = "nuvoton,numaker-spi"; 374 reg = <0x40068000 0x6c>; 375 interrupts = <77 0>; 376 resets = <&rst NUMAKER_SPI7_RST>; 377 clocks = <&pcc NUMAKER_SPI7_MODULE NUMAKER_CLK_CLKSEL4_SPI7SEL_HIRC 0>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 status = "disabled"; 381 }; 382 383 spi8: spi@4006b000 { 384 compatible = "nuvoton,numaker-spi"; 385 reg = <0x4006b000 0x6c>; 386 interrupts = <108 0>; 387 resets = <&rst NUMAKER_SPI8_RST>; 388 clocks = <&pcc NUMAKER_SPI8_MODULE NUMAKER_CLK_CLKSEL4_SPI8SEL_HIRC 0>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 status = "disabled"; 392 }; 393 394 spi9: spi@4006c000 { 395 compatible = "nuvoton,numaker-spi"; 396 reg = <0x4006c000 0x6c>; 397 interrupts = <111 0>; 398 resets = <&rst NUMAKER_SPI9_RST>; 399 clocks = <&pcc NUMAKER_SPI9_MODULE NUMAKER_CLK_CLKSEL4_SPI9SEL_HIRC 0>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 spi10: spi@4006d000 { 406 compatible = "nuvoton,numaker-spi"; 407 reg = <0x4006d000 0x6c>; 408 interrupts = <119 0>; 409 resets = <&rst NUMAKER_SPI10_RST>; 410 clocks = <&pcc NUMAKER_SPI10_MODULE NUMAKER_CLK_CLKSEL4_SPI10SEL_HIRC 0>; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 status = "disabled"; 414 }; 415 416 epwm0: epwm@40058000 { 417 compatible = "nuvoton,numaker-pwm"; 418 reg = <0x40058000 0x37c>; 419 interrupts = <25 0>, <26 0>, <27 0>; 420 interrupt-names = "pair0", "pair1", "pair2"; 421 resets = <&rst NUMAKER_EPWM0_RST>; 422 prescaler = <19>; 423 clocks = <&pcc NUMAKER_EPWM0_MODULE NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0 0>; 424 #pwm-cells = <3>; 425 status = "disabled"; 426 }; 427 428 epwm1: epwm@40059000 { 429 compatible = "nuvoton,numaker-pwm"; 430 reg = <0x40059000 0x37c>; 431 interrupts = <29 0>, <30 0>, <31 0>; 432 interrupt-names = "pair0", "pair1", "pair2"; 433 resets = <&rst NUMAKER_EPWM1_RST>; 434 prescaler = <19>; 435 clocks = <&pcc NUMAKER_EPWM1_MODULE NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1 0>; 436 #pwm-cells = <3>; 437 status = "disabled"; 438 }; 439 440 canfd0: canfd@40020000 { 441 compatible = "nuvoton,numaker-canfd"; 442 reg = <0x40020000 0x200>, <0x40020200 0x1800>; 443 reg-names = "m_can", "message_ram"; 444 interrupts = <112 0>, <113 0>; 445 interrupt-names = "int0", "int1"; 446 resets = <&rst NUMAKER_CANFD0_RST>; 447 clocks = <&pcc NUMAKER_CANFD0_MODULE 448 NUMAKER_CLK_CLKSEL0_CANFD0SEL_HCLK 449 NUMAKER_CLK_CLKDIV5_CANFD0(1)>; 450 bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; 451 status = "disabled"; 452 }; 453 454 canfd1: canfd@40024000 { 455 compatible = "nuvoton,numaker-canfd"; 456 reg = <0x40024000 0x200>, <0x40024200 0x1800>; 457 reg-names = "m_can", "message_ram"; 458 interrupts = <114 0>, <115 0>; 459 interrupt-names = "int0", "int1"; 460 resets = <&rst NUMAKER_CANFD1_RST>; 461 clocks = <&pcc NUMAKER_CANFD1_MODULE 462 NUMAKER_CLK_CLKSEL0_CANFD1SEL_HCLK 463 NUMAKER_CLK_CLKDIV5_CANFD1(1)>; 464 bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; 465 status = "disabled"; 466 }; 467 468 canfd2: canfd@40028000 { 469 compatible = "nuvoton,numaker-canfd"; 470 reg = <0x40028000 0x200>, <0x40028200 0x1800>; 471 reg-names = "m_can", "message_ram"; 472 interrupts = <120 0>, <121 0>; 473 interrupt-names = "int0", "int1"; 474 resets = <&rst NUMAKER_CANFD2_RST>; 475 clocks = <&pcc NUMAKER_CANFD2_MODULE 476 NUMAKER_CLK_CLKSEL0_CANFD2SEL_HCLK 477 NUMAKER_CLK_CLKDIV5_CANFD2(1)>; 478 bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; 479 status = "disabled"; 480 }; 481 482 canfd3: canfd@4002c000 { 483 compatible = "nuvoton,numaker-canfd"; 484 reg = <0x4002c000 0x200>, <0x4002c200 0x1800>; 485 reg-names = "m_can", "message_ram"; 486 interrupts = <122 0>, <123 0>; 487 interrupt-names = "int0", "int1"; 488 resets = <&rst NUMAKER_CANFD3_RST>; 489 clocks = <&pcc NUMAKER_CANFD3_MODULE 490 NUMAKER_CLK_CLKSEL0_CANFD3SEL_HCLK 491 NUMAKER_CLK_CLKDIV5_CANFD3(1)>; 492 bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; 493 status = "disabled"; 494 }; 495 496 emac: ethernet@40012000 { 497 compatible = "nuvoton,numaker-ethernet"; 498 reg = <0x40012000 0x105C>; 499 interrupts = <66 0>; 500 resets = <&rst NUMAKER_EMAC0_RST>; 501 phy-addr = <1>; 502 clocks = <&pcc NUMAKER_EMAC0_MODULE 0 0>; 503 status = "disabled"; 504 }; 505 506 i2c0: i2c@40080000 { 507 compatible = "nuvoton,numaker-i2c"; 508 clock-frequency = <I2C_BITRATE_STANDARD>; 509 reg = <0x40080000 0x1000>; 510 interrupts = <38 0>; 511 resets = <&rst NUMAKER_I2C0_RST>; 512 clocks = <&pcc NUMAKER_I2C0_MODULE 0 0>; 513 status = "disabled"; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 }; 517 518 i2c1: i2c@40081000 { 519 compatible = "nuvoton,numaker-i2c"; 520 clock-frequency = <I2C_BITRATE_STANDARD>; 521 reg = <0x40081000 0x1000>; 522 interrupts = <39 0>; 523 resets = <&rst NUMAKER_I2C1_RST>; 524 clocks = <&pcc NUMAKER_I2C1_MODULE 0 0>; 525 status = "disabled"; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 }; 529 530 i2c2: i2c@40082000 { 531 compatible = "nuvoton,numaker-i2c"; 532 clock-frequency = <I2C_BITRATE_STANDARD>; 533 reg = <0x40082000 0x1000>; 534 interrupts = <82 0>; 535 resets = <&rst NUMAKER_I2C2_RST>; 536 clocks = <&pcc NUMAKER_I2C2_MODULE 0 0>; 537 status = "disabled"; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 }; 541 542 i2c3: i2c@40083000 { 543 compatible = "nuvoton,numaker-i2c"; 544 clock-frequency = <I2C_BITRATE_STANDARD>; 545 reg = <0x40083000 0x1000>; 546 interrupts = <83 0>; 547 resets = <&rst NUMAKER_I2C3_RST>; 548 clocks = <&pcc NUMAKER_I2C3_MODULE 0 0>; 549 status = "disabled"; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 }; 553 554 i2c4: i2c@40084000 { 555 compatible = "nuvoton,numaker-i2c"; 556 clock-frequency = <I2C_BITRATE_STANDARD>; 557 reg = <0x40084000 0x1000>; 558 interrupts = <118 0>; 559 resets = <&rst NUMAKER_I2C4_RST>; 560 clocks = <&pcc NUMAKER_I2C4_MODULE 0 0>; 561 status = "disabled"; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 }; 565 566 eadc0: eadc@40043000 { 567 compatible = "nuvoton,numaker-adc"; 568 reg = <0x40043000 0xffc>; 569 interrupts = <42 0>; 570 resets = <&rst NUMAKER_EADC0_RST>; 571 clocks = <&pcc NUMAKER_EADC0_MODULE 572 NUMAKER_CLK_CLKSEL0_EADC0SEL_HCLK 573 NUMAKER_CLK_CLKDIV0_EADC0(12)>; 574 channels = <19>; 575 status = "disabled"; 576 #io-channel-cells = <1>; 577 }; 578 579 eadc1: eadc@4004b000 { 580 compatible = "nuvoton,numaker-adc"; 581 reg = <0x4004b000 0xffc>; 582 interrupts = <104 0>; 583 resets = <&rst NUMAKER_EADC1_RST>; 584 clocks = <&pcc NUMAKER_EADC1_MODULE 585 NUMAKER_CLK_CLKSEL0_EADC1SEL_HCLK 586 NUMAKER_CLK_CLKDIV2_EADC1(12)>; 587 channels = <19>; 588 status = "disabled"; 589 #io-channel-cells = <1>; 590 }; 591 592 eadc2: eadc@40097000 { 593 compatible = "nuvoton,numaker-adc"; 594 reg = <0x40097000 0xffc>; 595 interrupts = <124 0>; 596 resets = <&rst NUMAKER_EADC2_RST>; 597 clocks = <&pcc NUMAKER_EADC2_MODULE 598 NUMAKER_CLK_CLKSEL0_EADC2SEL_HCLK 599 NUMAKER_CLK_CLKDIV5_EADC2(12)>; 600 channels = <19>; 601 status = "disabled"; 602 #io-channel-cells = <1>; 603 }; 604 605 usbd: usbd@400c0000 { 606 compatible = "nuvoton,numaker-usbd"; 607 reg = <0x400c0000 0x1000>; 608 interrupts = <53 0>; 609 resets = <&rst NUMAKER_USBD_RST>; 610 clocks = <&pcc NUMAKER_USBD_MODULE NUMAKER_CLK_CLKSEL0_USBSEL_HIRC48M 611 NUMAKER_CLK_CLKDIV0_USB(1)>; 612 dma-buffer-size = <1536>; 613 status = "disabled"; 614 num-bidir-endpoints = <25>; 615 disallow-iso-in-out-same-number; 616 }; 617 618 wwdt: watchdog@40040100 { 619 compatible = "nuvoton,numaker-wwdt"; 620 reg = <0x40040100 0x10>; 621 interrupts = <9 0>; 622 clocks = <&pcc NUMAKER_WWDT_MODULE NUMAKER_CLK_CLKSEL1_WWDTSEL_LIRC 0>; 623 status = "disabled"; 624 }; 625 626 rtc: rtc@40041000 { 627 compatible = "nuvoton,numaker-rtc"; 628 reg = <0x40041000 0x138>; 629 interrupts = <6 0>; 630 oscillator = "lxt"; 631 clocks = <&pcc NUMAKER_RTC_MODULE 0 0>; 632 alarms-count = <1>; 633 }; 634 }; 635}; 636 637&nvic { 638 arm,num-irq-priority-bits = <4>; 639}; 640
