1/*
2 * Copyright 2023-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/clock/scg_k4.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/pwm/pwm.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14
15/ {
16	aliases {
17		watchdog0 = &wdog0;
18	};
19
20	chosen {
21		zephyr,bt-hci = &hci;
22		zephyr,nbu = &nbu;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu0: cpu@0 {
30			compatible = "arm,cortex-m33f";
31			reg = <0>;
32			#address-cells = <1>;
33			#size-cells = <1>;
34
35			mpu: mpu@e000ed90 {
36				compatible = "arm,armv8m-mpu";
37				reg = <0xe000ed90 0x40>;
38			};
39		};
40	};
41
42	soc {
43		fmu: memory-controller@50020000 {
44			ranges = <0x0 0x10000000 DT_SIZE_M(1)>;
45			#address-cells = <1>;
46			#size-cells = <1>;
47			compatible = "nxp,msf1";
48			reg = <0x50020000 0x1000>;
49			interrupts = <27 0>;
50			status = "disabled";
51
52			flash: flash@0 {
53				reg = <0x0 DT_SIZE_M(1)>;
54				compatible = "soc-nv-flash";
55				write-block-size = <16>;
56				erase-block-size = <8192>;
57			};
58		};
59
60		ctcm: sram@14000000 {
61			ranges = <0x0 0x14000000 DT_SIZE_K(16)>;
62			#address-cells = <1>;
63			#size-cells = <1>;
64
65			ctcm0: code_memory@0 {
66				compatible = "mmio-sram";
67				reg = <0x0 DT_SIZE_K(16)>;
68			};
69		};
70
71		stcm: sram@30000000 {
72			ranges = <0x0 0x30000000 DT_SIZE_K(112)>;
73			#address-cells = <1>;
74			#size-cells = <1>;
75
76			stcm0: system_memory@0 {
77				compatible = "mmio-sram";
78				/* With only the first 64KB having ECC */
79				reg = <0x0 DT_SIZE_K(104)>;
80			};
81
82			stcm1: system_memory@1a000 {
83				compatible = "zephyr,memory-region","mmio-sram";
84				reg = <0x1a000 DT_SIZE_K(8)>;
85				zephyr,memory-region = "RetainedMem";
86			};
87		};
88
89		smu2: sram@489c0000 {
90			ranges = <0x0 0x489c0000 DT_SIZE_K(40)>;
91		};
92
93		peripheral: peripheral@50000000 {
94			ranges = <0x0 0x50000000 0x10000000>;
95			#address-cells = <1>;
96			#size-cells = <1>;
97
98			pbridge2: pbridge2@0 {
99				ranges = <>;
100				reg = <0x0 0x4b000>;
101				#address-cells = <1>;
102				#size-cells = <1>;
103			};
104
105			fast_peripheral0: fast_peripherals0@8000000 {
106				#address-cells = <1>;
107				#size-cells = <1>;
108				ranges = <0x0 0x8000000 0x40000>;
109			};
110
111			fast_peripheral1: fast_peripherals1@8800000 {
112				#address-cells = <1>;
113				#size-cells = <1>;
114				ranges = <0x0 0x8800000 0x210000>;
115			};
116		};
117	};
118
119	pinctrl: pinctrl {
120		compatible = "nxp,port-pinctrl";
121	};
122};
123
124&nvic {
125	arm,num-irq-priority-bits = <3>;
126};
127
128&smu2 {
129	#address-cells = <1>;
130	#size-cells = <1>;
131
132	rpmsgmem: memory@8800 {
133		compatible = "zephyr,memory-region","mmio-sram";
134		reg = <0x8800 DT_SIZE_K(6)>;
135		zephyr,memory-region = "rpmsg_sh_mem";
136		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
137	};
138};
139
140&pbridge2 {
141	#address-cells = <1>;
142	#size-cells = <1>;
143
144	scg: clock-controller@1e000 {
145		compatible = "nxp,scg-k4";
146		reg = <0x1e000 0x404>;
147		#clock-cells = <2>;
148	};
149
150	porta: pinctrl@42000 {
151		compatible = "nxp,port-pinmux";
152		reg = <0x42000 0xe0>;
153		clocks = <&scg SCG_K4_SLOW_CLK 0x108>;
154	};
155
156	portb: pinctrl@43000 {
157		compatible = "nxp,port-pinmux";
158		reg = <0x43000 0xe0>;
159		clocks = <&scg SCG_K4_SLOW_CLK 0x10c>;
160	};
161
162	portc: pinctrl@44000 {
163		compatible = "nxp,port-pinmux";
164		reg = <0x44000 0xe0>;
165		clocks = <&scg SCG_K4_SLOW_CLK 0x110>;
166	};
167
168	portd: pinctrl@45000 {
169		compatible = "nxp,port-pinmux";
170		reg = <0x45000 0xe0>;
171		clocks = <&scg SCG_K4_SLOW_CLK 0>;
172	};
173
174	lpuart0: serial@38000 {
175		compatible = "nxp,lpuart";
176		reg = <0x38000 0x34>;
177		interrupts = <44 0>;
178		clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
179		status = "disabled";
180	};
181
182	lpuart1: serial@39000 {
183		compatible = "nxp,lpuart";
184		reg = <0x39000 0x34>;
185		interrupts = <45 0>;
186		clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
187		status = "disabled";
188	};
189
190	lpi2c0: i2c@33000 {
191		compatible = "nxp,lpi2c";
192		clock-frequency = <I2C_BITRATE_STANDARD>;
193		#address-cells = <1>;
194		#size-cells = <0>;
195		reg = <0x33000 0x200>;
196		interrupts = <39 0>;
197		clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
198		status = "disabled";
199	};
200
201	lpi2c1: i2c@34000 {
202		compatible = "nxp,lpi2c";
203		clock-frequency = <I2C_BITRATE_STANDARD>;
204		#address-cells = <1>;
205		#size-cells = <0>;
206		reg = <0x34000 0x200>;
207		interrupts = <40 0>;
208		clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
209		status = "disabled";
210	};
211
212	lpspi0: spi@36000 {
213		compatible = "nxp,lpspi";
214		reg = <0x36000 0x800>;
215		interrupts = <42 0>;
216		clocks = <&scg SCG_K4_FIRC_CLK 0xd8>;
217		#address-cells = <1>;
218		#size-cells = <0>;
219		status = "disabled";
220	};
221
222	lpspi1: spi@37000 {
223		compatible = "nxp,lpspi";
224		reg = <0x37000 0x800>;
225		interrupts = <43 0>;
226		clocks = <&scg SCG_K4_FIRC_CLK 0xdc>;
227		#address-cells = <1>;
228		#size-cells = <0>;
229		status = "disabled";
230	};
231
232	gpiod: gpio@46000{
233		compatible = "nxp,kinetis-gpio";
234		status = "disabled";
235		gpio-controller;
236		#gpio-cells = <2>;
237		nxp,kinetis-port = <&portd>;
238		reg = <0x46000 0x128>;
239		interrupts = <65 0>, <66 0>;
240	};
241
242	vbat: vbat@2b000 {
243		reg = <0x2b000 0x400>;
244		interrupts = <74 0>;
245	};
246
247	tpm0: pwm@31000 {
248		compatible = "nxp,kinetis-tpm";
249		reg = <0x31000 0x100>;
250		interrupts = <37 0>;
251		clocks = <&scg SCG_K4_FIRC_CLK 0xc4>;
252		prescaler = <16>;
253		status = "disabled";
254		#pwm-cells = <3>;
255	};
256
257	tpm1: pwm@32000 {
258		compatible = "nxp,kinetis-tpm";
259		reg = <0x32000 0x100>;
260		interrupts = <38 0>;
261		clocks = <&scg SCG_K4_FIRC_CLK 0xc8>;
262		prescaler = <16>;
263		status = "disabled";
264		#pwm-cells = <3>;
265	};
266
267	wdog0: watchdog@1a000 {
268		compatible = "nxp,wdog32";
269		reg = <0x1a000 16>;
270		interrupts = <23 0>;
271		clocks = <&scg SCG_K4_SYSOSC_CLK 0x68>;
272		clk-source = <1>;
273		clk-divider = <256>;
274		status = "okay";
275	};
276
277	wdog1: watchdog@1b000 {
278		compatible = "nxp,wdog32";
279		reg = <0x1b000 16>;
280		interrupts = <24 0>;
281		clocks = <&scg SCG_K4_SYSOSC_CLK 0x6c>;
282		clk-source = <1>;
283		clk-divider = <256>;
284		status = "disabled";
285	};
286
287	lptmr0: timer@2d000 {
288		compatible = "nxp,lptmr";
289		reg = <0x2d000 0x10>;
290		interrupts = <34 0>;
291		clock-frequency = <32000>;
292		clk-source = <2>;
293		prescaler = <1>;
294		resolution = <32>;
295		status = "disabled";
296	};
297
298	lptmr1: timer@2e000 {
299		compatible = "nxp,lptmr";
300		reg = <0x2e000 0x10>;
301		interrupts = <35 0>;
302		clock-frequency = <32000>;
303		clk-source = <2>;
304		prescaler = <1>;
305		resolution = <32>;
306		status = "disabled";
307	};
308
309	nbu: nbu {
310		compatible = "nxp,nbu";
311		interrupts = <48 2>;
312		interrupt-names = "nbu_rx_int";
313	};
314
315	hci: hci_ble {
316		compatible = "nxp,hci-ble";
317	};
318
319	flexcan0: can@3b000 {
320		compatible = "nxp,flexcan";
321		reg = <0x3b000 0x3080>;
322		interrupts = <47 0>;
323		interrupt-names = "common";
324		clocks = <&scg SCG_K4_FIRC_CLK 0xec>;
325		clk-source = <2>;
326		status = "disabled";
327	};
328
329	adc0: adc@47000 {
330		compatible = "nxp,lpc-lpadc";
331		reg = <0x47000 0x1000>;
332		interrupts = <71 0>;
333		clocks = <&scg SCG_K4_FIRC_CLK 0x11c>;
334		voltage-ref= <1>;
335		calibration-average = <128>;
336		/* pwrlvl 0 is slow speed low power, 1 is opposite */
337		power-level = <0>;
338		offset-value-a = <0>;
339		offset-value-b = <0>;
340		#io-channel-cells = <1>;
341		nxp,references = <&vref 1800>;
342		status = "disabled";
343	};
344
345	vref: regulator@4a000 {
346		compatible = "nxp,vref";
347		regulator-name = "mcxw71-vref";
348		reg = <0x4a000 0x20>;
349		#nxp,reference-cells = <1>;
350		nxp,buffer-startup-delay-us = <400>;
351		nxp,bandgap-startup-time-us = <20>;
352		regulator-min-microvolt = <1000000>;
353		regulator-max-microvolt = <2100000>;
354		nxp,current-compensation-en;
355		status = "disabled";
356	};
357};
358
359&fast_peripheral0 {
360	gpioa: gpio@10000{
361		compatible = "nxp,kinetis-gpio";
362		status = "disabled";
363		gpio-controller;
364		#gpio-cells = <2>;
365		nxp,kinetis-port = <&porta>;
366		reg = <0x10000 0x128>;
367		interrupts = <59 0>, <60 0>;
368	};
369
370	gpiob: gpio@20000{
371		compatible = "nxp,kinetis-gpio";
372		status = "disabled";
373		gpio-controller;
374		#gpio-cells = <2>;
375		nxp,kinetis-port = <&portb>;
376		reg = <0x20000 0x128>;
377		interrupts = <61 0>, <62 0>;
378	};
379
380	gpioc: gpio@30000{
381		compatible = "nxp,kinetis-gpio";
382		status = "disabled";
383		gpio-controller;
384		#gpio-cells = <2>;
385		nxp,kinetis-port = <&portc>;
386		reg = <0x30000 0x128>;
387		interrupts = <63 0>, <64 0>;
388	};
389};
390