Searched refs:core_desc (Results 1 – 2 of 2) sorted by relevance
128 static struct core_state core_desc[CONFIG_MP_MAX_NUM_CPUS] = {{0}}; variable141 core_desc[core_id].ps = XTENSA_RSR("PS"); in _save_core_context()142 core_desc[core_id].vecbase = XTENSA_RSR("VECBASE"); in _save_core_context()143 core_desc[core_id].excsave2 = XTENSA_RSR("EXCSAVE2"); in _save_core_context()144 core_desc[core_id].excsave3 = XTENSA_RSR("EXCSAVE3"); in _save_core_context()145 core_desc[core_id].thread_ptr = XTENSA_RUR("THREADPTR"); in _save_core_context()147 core_desc[core_id].misc[0] = XTENSA_RSR("MISC0"); in _save_core_context()148 core_desc[core_id].misc[1] = XTENSA_RSR("MISC1"); in _save_core_context()150 __asm__ volatile("mov %0, a0" : "=r"(core_desc[core_id].a0)); in _save_core_context()151 __asm__ volatile("mov %0, a1" : "=r"(core_desc[core_id].a1)); in _save_core_context()[all …]
64 static struct core_state core_desc[CONFIG_MP_MAX_NUM_CPUS] = {{0}}; variable87 core_desc[core_id].ps = XTENSA_RSR("PS"); in _save_core_context()88 core_desc[core_id].excsave2 = XTENSA_RSR(ZSR_CPU_STR); in _save_core_context()89 __asm__ volatile("mov %0, a0" : "=r"(core_desc[core_id].a0)); in _save_core_context()90 __asm__ volatile("mov %0, a1" : "=r"(core_desc[core_id].a1)); in _save_core_context()91 sys_cache_data_flush_range(&core_desc[core_id], sizeof(struct core_state)); in _save_core_context()98 XTENSA_WSR("PS", core_desc[core_id].ps); in _restore_core_context()99 XTENSA_WSR(ZSR_CPU_STR, core_desc[core_id].excsave2); in _restore_core_context()100 __asm__ volatile("mov a0, %0" :: "r"(core_desc[core_id].a0)); in _restore_core_context()101 __asm__ volatile("mov a1, %0" :: "r"(core_desc[core_id].a1)); in _restore_core_context()[all …]
