| /Zephyr-latest/soc/nordic/common/vpr/ |
| D | soc_isr_stacking.h | 93 addi t1, sp, __struct_arch_esf_soc_context_OFFSET; \
99 addi t1, sp, __struct_arch_esf_soc_context_OFFSET; \
114 addi sp, sp, -ESF_SW_EXC_SIZEOF; \
119 addi sp, sp, -ESF_SW_IRQ_SIZEOF; \
131 addi sp, sp, ESF_SW_EXC_SIZEOF; \
135 addi sp, sp, ESF_SW_IRQ_SIZEOF; \
|
| /Zephyr-latest/soc/telink/tlsr/tlsr951x/ |
| D | start.S | 52 addi t2, t2, 4
63 addi t1, t1, 4
64 addi t2, t2, 4
75 addi t1, t1, 4
76 addi t2, t2, 4
|
| /Zephyr-latest/soc/intel/intel_adsp/ace/ |
| D | asm_memory_management.h | 37 addi \az, \az, DT_REG_SIZE(DT_NODELABEL(lsbpm))
38 addi \au, \au, -1 /* Decrement bank count */
59 addi \az, \az, DT_REG_SIZE(DT_NODELABEL(hsbpm)) /* Move to next bank control register */
60 addi \au, \au, -1 /* Decrement bank count */
|
| /Zephyr-latest/arch/xtensa/core/ |
| D | xtensa_asm2_util.S | 61 addi a1, a1, -16
68 addi a1, a1, -16
75 addi a1, a1, -16
86 addi a1, a1, -4
104 addi a1, a1, 4
108 addi a2, a2, -16
115 addi a2, a2, -16
122 addi a2, a2, -16
192 addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF
237 addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF
[all …]
|
| D | crt1.S | 168 addi a6, a6, 8 /* next entry */
172 addi a8, a8, 4
176 addi a8, a8, 8
183 addi a8, a8, 16
|
| D | xtensa_hifi.S | 26 addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1)
47 addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1)
|
| D | userspace.S | 33 addi a2, a2, 3
60 addi a0, a0, -___xtensa_irq_bsa_t_SIZEOF
94 addi a0, a0, -___xtensa_irq_bsa_t_SIZEOF
105 addi a3, a3, 3
109 addi a2, a2, -1
118 addi a3, a3, 3
178 addi a1, a1, -4
198 addi a1, a1, 4
289 addi a1, a1, -28
|
| D | debug_helpers_asm.S | 37 addi a6, a6, ___xtensa_irq_bsa_t_SIZEOF
|
| /Zephyr-latest/soc/common/riscv-privileged/ |
| D | vector.S | 45 addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */
78 addi t0, t0, 0x01 /* Enable vectored mode by setting LSB */
88 addi t0, t0, 0x03 /* Set mode bits to 3, signifying CLIC. Everything else is reserved. */
|
| /Zephyr-latest/soc/espressif/esp32c2/ |
| D | soc_irq.S | 14 addi sp, sp,-4
19 addi sp, sp, 4
|
| /Zephyr-latest/soc/espressif/esp32c3/ |
| D | soc_irq.S | 14 addi sp, sp,-4
19 addi sp, sp, 4
|
| /Zephyr-latest/soc/espressif/esp32c6/ |
| D | soc_irq.S | 20 addi sp, sp,-4
25 addi sp, sp, 4
|
| /Zephyr-latest/arch/riscv/core/ |
| D | isr.S | 193 addi sp, sp, -__struct_arch_esf_SIZEOF
314 addi a0, sp, __struct_arch_esf_soc_context_OFFSET
399 addi t0, t0, 4
463 addi sp, sp, -__callee_saved_t_SIZEOF
491 addi t2, t1, 1
500 addi sp, sp, -16
530 addi t1, t1, 4
543 addi sp, sp, -4
570 addi sp, sp, 4
607 addi t2, t1, 1
[all …]
|
| D | pmp.S | 69 addi a1, a1, RV_REGSIZE - 1
80 addi a0, a0, 1
|
| /Zephyr-latest/arch/nios2/core/ |
| D | swap.S | 26 addi sp, sp, -12
36 addi sp, sp, 12
127 addi sp, sp, -20
141 addi sp, sp, 20
164 addi sp, sp, 16
|
| D | crt0.S | 119 addi r1, r1, 4
129 addi sp, sp, CONFIG_ISR_STACK_SIZE
|
| D | exception.S | 65 addi r15, ea, -4
100 addi sp, sp, -4
224 addi sp, sp, __struct_arch_esf_SIZEOF
|
| /Zephyr-latest/soc/intel/intel_adsp/cavs/ |
| D | power_down_cavs.S | 92 addi temp_reg0, temp_reg0, -1
123 addi temp_reg0, temp_reg0, -1
145 addi temp_reg0, temp_reg0, -1
|
| D | asm_ldo_management.h | 28 addi \ax, \ax, -1
71 addi \ax, \ax, -1
91 addi \ax, \ax, -1
|
| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_nuclei_eclic.S | 37 addi sp, sp, -16
78 addi sp, sp, 16
|
| /Zephyr-latest/soc/neorv32/ |
| D | reset.S | 57 addi x8, x8, 4
71 addi x5, x5, 4
|
| /Zephyr-latest/arch/xtensa/core/startup/ |
| D | reset_vector.S | 249 addi a5, a7, - PWRSTAT_WAKEUP_RESET
414 addi a10, a9, 1 /* set that new bit if... */
417 addi a8, a8, -5 /* make valid attrib indices negative */
424 addi a6, a6, -1
486 addi a2, a2, 12
489 addi a5, a5, 4
491 addi a3, a3, 4
|
| /Zephyr-latest/tests/arch/xtensa/save_restore_hifi/src/ |
| D | hifi.S | 24 addi a2, a2, 64
54 addi a2, a2, 64
|
| /Zephyr-latest/arch/xtensa/include/ |
| D | xtensa_asm2_s.h | 364 addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF
504 addi a0, a0, 1
510 addi a0, a0, 1
526 addi a0, a0, -1
542 addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF
578 addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF
678 addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF
|
| /Zephyr-latest/arch/mips/core/ |
| D | isr.S | 61 addi sp, sp, -__struct_arch_esf_SIZEOF ;\
66 addi sp, sp, __struct_arch_esf_SIZEOF ;
139 addi k0, k0, 4
180 addi sp, sp, -16
|
