| /trusted-firmware-a-latest/drivers/st/clk/ |
| D | clk-stm32-core.c | 61 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_oscillator_get_data() local
62 struct stm32_osc_cfg *osc_cfg = clk->clock_cfg; in clk_oscillator_get_data()
161 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_gate_enable() local
162 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_enable()
171 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_gate_disable() local
172 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_disable()
179 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_gate_is_enabled() local
180 struct clk_gate_cfg *cfg = clk->clock_cfg; in clk_gate_is_enabled()
298 int _clk_stm32_set_parent(struct stm32_clk_priv *priv, int clk, int clkp) in _clk_stm32_set_parent() argument
305 pid = priv->clks[clk].parent; in _clk_stm32_set_parent()
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| /trusted-firmware-a-latest/drivers/nxp/ddr/nxp-ddr/ |
| D | regs.c | 18 static inline unsigned int cal_cwl(const unsigned long clk) in cal_cwl() argument
20 const unsigned int mclk_ps = get_memory_clk_ps(clk); in cal_cwl()
89 static void cal_timing_cfg(const unsigned long clk, in cal_timing_cfg() argument
97 const unsigned int mclk_ps = get_memory_clk_ps(clk); in cal_timing_cfg()
108 int trwt_mclk = (clk / 1000000 > 1900) ? 3 : 2; in cal_timing_cfg()
112 const int act_pd_exit_mclk = picos_to_mclk(clk, txp); in cal_timing_cfg()
119 const int tmrd_mclk = max(24U, picos_to_mclk(clk, 15000)); in cal_timing_cfg()
120 const int pretoact_mclk = picos_to_mclk(clk, pdimm->trp_ps); in cal_timing_cfg()
121 const int acttopre_mclk = picos_to_mclk(clk, pdimm->tras_ps); in cal_timing_cfg()
122 const int acttorw_mclk = picos_to_mclk(clk, pdimm->trcd_ps); in cal_timing_cfg()
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| D | ddr.c | 262 static int cal_odt(const unsigned int clk, in cal_odt() argument
323 static int cal_opts(const unsigned int clk, in cal_opts() argument
375 popts->bstopre = picos_to_mclk(clk, pdimm->refresh_rate_ps) >> 2; in cal_opts()
436 const unsigned long speed = priv->clk / 1000000; in cal_board_params()
478 ret = cal_odt(priv->clk, in synthesize_ctlr()
487 ret = cal_opts(priv->clk, in synthesize_ctlr()
805 ret = compute_ddrc(priv->clk, in cal_ddrc_regs()
826 ret = ddrc_set_regs(priv->clk, &priv->ddr_reg, priv->ddr[i], 0); in write_ddrc_regs()
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| /trusted-firmware-a-latest/drivers/imx/usdhc/ |
| D | imx_usdhc.c | 22 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width);
39 static void imx_usdhc_set_clk(int clk) in imx_usdhc_set_clk() argument
46 assert(clk > 0); in imx_usdhc_set_clk()
48 while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256) in imx_usdhc_set_clk()
51 while (sdhc_clk / div > clk && div < 16) in imx_usdhc_set_clk()
56 clk = (pre_div << 8) | (div << 4); in imx_usdhc_set_clk()
59 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk); in imx_usdhc_set_clk()
254 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width) in imx_usdhc_set_ios() argument
258 imx_usdhc_set_clk(clk); in imx_usdhc_set_ios()
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| /trusted-firmware-a-latest/plat/intel/soc/common/include/ |
| D | socfpga_private.h | 14 #define EMMC_INIT_PARAMS(base, clk) \ argument
16 .clk_rate = (clk), \
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| /trusted-firmware-a-latest/plat/imx/common/include/sci/svc/pm/ |
| D | sci_pm_api.h | 454 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
475 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
503 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
527 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
548 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
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| /trusted-firmware-a-latest/include/drivers/nxp/ddr/ |
| D | ddr.h | 89 unsigned long clk; member
128 int compute_ddrc(const unsigned long clk,
135 int ddrc_set_regs(const unsigned long clk,
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| D | utility.h | 19 unsigned int get_memory_clk_ps(unsigned long clk);
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| /trusted-firmware-a-latest/drivers/renesas/common/ddr/ddr_b/ |
| D | boot_init_dram_config.c | 1770 void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) in boardcnf_get_brd_clk() argument
1775 *clk = 50; in boardcnf_get_brd_clk()
1781 *clk = 50; in boardcnf_get_brd_clk()
1785 *clk = 60; in boardcnf_get_brd_clk()
1789 *clk = 75; in boardcnf_get_brd_clk()
1793 *clk = 100; in boardcnf_get_brd_clk()
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| /trusted-firmware-a-latest/plat/nxp/soc-ls1046a/ls1046ardb/ |
| D | ddr_init.c | 171 const unsigned long clk = priv->clk / 1000000; in board_static_ddr() local
176 if (table[i].rate >= clk) { in board_static_ddr()
186 ERROR("Not static settings for rate %ld\n", clk); in board_static_ddr()
252 info.clk = get_ddr_freq(&sys, 0); in init_ddr()
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| /trusted-firmware-a-latest/plat/imx/common/sci/svc/pm/ |
| D | pm_rpc_clnt.c | 236 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) in sc_pm_set_clock_rate() argument
246 RPC_U8(&msg, 6U) = (uint8_t)clk; in sc_pm_set_clock_rate()
257 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) in sc_pm_get_clock_rate() argument
266 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_get_clock_rate()
280 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog) in sc_pm_clock_enable() argument
289 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_clock_enable()
301 sc_pm_clk_t clk, sc_pm_clk_parent_t parent) in sc_pm_set_clock_parent() argument
310 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_set_clock_parent()
321 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent) in sc_pm_get_clock_parent() argument
330 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_get_clock_parent()
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| /trusted-firmware-a-latest/plat/intel/soc/common/drivers/sdmmc/ |
| D | sdmmc.h | 38 int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
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| D | sdmmc.c | 211 static int sdmmc_set_ios(unsigned int clk, unsigned int bus_width) in sdmmc_set_ios() argument
235 return ops->set_ios(clk, width); in sdmmc_set_ios()
463 static int sdmmc_enumerate(unsigned int clk, unsigned int bus_width) in sdmmc_enumerate() argument
537 ret = sdmmc_set_ios(clk, bus_width); in sdmmc_enumerate()
571 ret = ops->set_ios(clk, bus_width); in sdmmc_enumerate()
711 int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, in sd_or_mmc_init() argument
723 (clk != 0) && in sd_or_mmc_init()
734 return sdmmc_enumerate(clk, width); in sd_or_mmc_init()
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| /trusted-firmware-a-latest/plat/st/stm32mp1/ |
| D | stm32mp1_scmi.c | 459 struct stm32_scmi_clk *clk = &res->clock[j]; in stm32mp1_init_scmi_server() local
461 if ((clk->name == NULL) || in stm32mp1_init_scmi_server()
462 (strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE)) { in stm32mp1_init_scmi_server()
468 if (clk->enabled && in stm32mp1_init_scmi_server()
469 stm32mp_nsec_can_access_clock(clk->clock_id)) { in stm32mp1_init_scmi_server()
470 clk_enable(clk->clock_id); in stm32mp1_init_scmi_server()
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| /trusted-firmware-a-latest/drivers/synopsys/emmc/ |
| D | dw_mmc.c | 125 static int dw_set_ios(unsigned int clk, unsigned int width);
157 static void dw_set_clk(int clk) in dw_set_clk() argument
162 assert(clk > 0); in dw_set_clk()
165 if ((dw_params.clk_rate / (2 * div)) <= clk) { in dw_set_clk()
322 static int dw_set_ios(unsigned int clk, unsigned int width) in dw_set_ios() argument
338 dw_set_clk(clk); in dw_set_ios()
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| /trusted-firmware-a-latest/drivers/rpi3/sdhost/ |
| D | rpi3_sdhost.c | 22 static int rpi3_sdhost_set_ios(unsigned int clk, unsigned int width);
392 static int rpi3_sdhost_set_clock(unsigned int clk) in rpi3_sdhost_set_clock() argument
398 if (clk < 100000) { in rpi3_sdhost_set_clock()
404 div = max_clk / clk; in rpi3_sdhost_set_clock()
408 if ((max_clk / div) > clk) in rpi3_sdhost_set_clock()
424 static int rpi3_sdhost_set_ios(unsigned int clk, unsigned int width) in rpi3_sdhost_set_ios() argument
429 rpi3_sdhost_set_clock(clk); in rpi3_sdhost_set_ios()
430 VERBOSE("rpi3_sdhost: Changing clock to %dHz for data mode\n", clk); in rpi3_sdhost_set_ios()
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| /trusted-firmware-a-latest/plat/nxp/soc-lx2160a/lx2160ardb/ |
| D | ddr_init.c | 190 info.clk = get_ddr_freq(&sys, 0); in init_ddr()
193 if (info.clk == 0) { in init_ddr()
194 info.clk = get_ddr_freq(&sys, 1); in init_ddr()
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| /trusted-firmware-a-latest/drivers/st/uart/ |
| D | stm32_uart.c | 311 int clk; in stm32_uart_init() local
340 clk = fdt_get_clock_id(uart_node); in stm32_uart_init()
341 if (clk < 0) { in stm32_uart_init()
344 clk_enable(clk); in stm32_uart_init()
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| /trusted-firmware-a-latest/fdts/ |
| D | stm32mp251.dtsi | 28 clk_hse: clk-hse {
34 clk_hsi: clk-hsi {
40 clk_lse: clk-lse {
46 clk_lsi: clk-lsi {
52 clk_msi: clk-msi {
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| D | stm32mp13-pinctrl.dtsi | 35 sdmmc1_clk_pins_a: sdmmc1-clk-0 {
59 sdmmc2_clk_pins_a: sdmmc2-clk-0 {
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| /trusted-firmware-a-latest/drivers/mmc/ |
| D | mmc.c | 229 static int mmc_set_ios(unsigned int clk, unsigned int bus_width) in mmc_set_ios() argument
253 return ops->set_ios(clk, width); in mmc_set_ios()
476 static int mmc_enumerate(unsigned int clk, unsigned int bus_width) in mmc_enumerate() argument
550 ret = mmc_set_ios(clk, bus_width); in mmc_enumerate()
584 ret = ops->set_ios(clk, bus_width); in mmc_enumerate()
827 int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, in mmc_init() argument
839 (clk != 0) && in mmc_init()
850 return mmc_enumerate(clk, width); in mmc_init()
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| /trusted-firmware-a-latest/drivers/st/gpio/ |
| D | stm32_gpio.c | 109 int clk; in dt_set_gpio_config() local
162 clk = fdt_get_clock_id(bank_node); in dt_set_gpio_config()
163 if (clk < 0) { in dt_set_gpio_config()
168 assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank)); in dt_set_gpio_config()
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| /trusted-firmware-a-latest/plat/nxp/soc-ls1088a/ls1088aqds/ |
| D | ddr_init.c | 72 info.clk = get_ddr_freq(&sys, 0); in init_ddr()
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| /trusted-firmware-a-latest/plat/nxp/soc-ls1046a/ls1046aqds/ |
| D | ddr_init.c | 76 info.clk = get_ddr_freq(&sys, 0); in init_ddr()
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| /trusted-firmware-a-latest/plat/nxp/soc-ls1088a/ls1088ardb/ |
| D | ddr_init.c | 73 info.clk = get_ddr_freq(&sys, 0); in init_ddr()
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