Searched refs:MPIDR (Results 1 – 23 of 23) sorted by relevance
38 ldcopr r0, MPIDR65 ldcopr r0, MPIDR97 ldcopr r0, MPIDR
23 ldcopr r0, MPIDR
70 ldcopr r0, MPIDR84 ldcopr r0, MPIDR
53 ldcopr r2, MPIDR97 ldcopr r0, MPIDR
17 tree. It also uses an MPIDR to find a node in the tree. The assumption that19 code is not scalable. The use of an MPIDR also restricts the number of38 using an MPIDR. There is no requirement to perform state coordination while130 corresponding to the MPIDR. It will return an error (-1) if an MPIDR is passed132 platform API have changed since it is required to validate the passed MPIDR. It137 the index since there is no need to validate the MPIDR of the calling core.147 Dealing with holes in MPIDR allocation151 core power domains, for example, Juno and FVPs, the logic to convert an MPIDR to163 #. Implement more complex logic to convert a valid MPIDR to a core index while173 allow use of a simpler logic to convert an MPIDR to a core index.[all …]
2640 These macros accept the CPU's MPIDR value, or its ordinal position
25 ldcopr r0, MPIDR48 ldcopr r0, MPIDR
22 ldcopr r0, MPIDR
61 ldcopr r0, MPIDR
29 .. |MPIDR| replace:: :term:`MPIDR`
117 MPIDR
1104 This function validates the ``MPIDR`` of a CPU and converts it to an index,1106 case the ``MPIDR`` is invalid, this function returns -1. This function will only2436 ``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the2512 CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``2669 by the ``MPIDR`` (first argument). The generic code expects the platform to2896 domain. The target power domain is identified by using both ``MPIDR`` (first2915 the power state of a node (identified by the first parameter, the ``MPIDR``) in
1562 …- do not panic on illegal MPIDR ([8a6d0d2](https://review.trustedfirmware.org/plugins/gitiles/TF-A…5659 - Added helper to calculate the position shift from MPIDR6182 - Fixed initialization issues caused by incorrect MPIDR topology mapping7991 accessing MPIDR assume that the `MT` bit is set for the platform and access
88 ldcopr r1, MPIDR
170 ldcopr r0, MPIDR197 ldcopr r0, MPIDR
38 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag39 is set, the functions which deal with MPIDR assume that the ``MT`` bit in40 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
207 the ID of the SGI. The second parameter, ``target``, must be the MPIDR of the233 - ``INTR_ROUTING_MODE_PE`` means the interrupt is routed to the PE whose MPIDR
481 - *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping.
53 :param target_cpu: Contains copy of affinity fields in the MPIDR register
30 - ``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers.
219 DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR) in DEFINE_SYSREG_RW_FUNCS()
534 #define MPIDR p15, 0, c0, c0, 5 macro
136 like shifted affinity format for MPIDR, cannot be detected at build time
