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Searched refs:IABR (Results 1 – 8 of 8) sorted by relevance

/loramac-node-latest/src/boards/mcu/saml21/cmsis/
Dcore_cm3.h326 …__IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register … member
1412 …return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /*… in NVIC_GetActive()
Dcore_sc300.h326 …__IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register … member
1392 …return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /*… in NVIC_GetActive()
Dcore_cm4.h373 …__IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register … member
1564 …return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /*… in NVIC_GetActive()
Dcore_cm7.h388 …__IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register … member
1751 …return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /*… in NVIC_GetActive()
/loramac-node-latest/src/boards/mcu/stm32/cmsis/
Dcore_cm3.h393 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ member
1513 …return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)… in NVIC_GetActive()
Dcore_sc300.h393 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ member
1495 …return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)… in NVIC_GetActive()
Dcore_cm4.h461 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ member
1687 …return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)… in NVIC_GetActive()
Dcore_cm7.h476 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ member
1895 …return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)… in NVIC_GetActive()