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Searched refs:CCR (Results 1 – 25 of 74) sorted by relevance

123

/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_dma.h525 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
544 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
563 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_IsEnabledChannel()
598 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_ConfigTransfer()
624 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_SetDataTransferDirection()
648 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetDataTransferDirection()
673 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, in LL_DMA_SetMode()
695 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMode()
718 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, in LL_DMA_SetPeriphIncMode()
740 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
Dstm32l0xx_hal_dma.h444 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
451 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
583 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRU…
595 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERR…
607 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTE…
Dstm32l0xx_ll_adc.h1671 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock); in LL_ADC_SetCommonClock()
1700 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); in LL_ADC_GetCommonClock()
1721 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_LFMEN, Resolution); in LL_ADC_SetCommonFrequencyMode()
1737 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_LFMEN)); in LL_ADC_GetCommonFrequencyMode()
1780 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VLCDEN, PathInternal); in LL_ADC_SetCommonPathInternalCh()
1782 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal); in LL_ADC_SetCommonPathInternalCh()
1808 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VLCDEN)); in LL_ADC_GetCommonPathInternalCh()
1810 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN)); in LL_ADC_GetCommonPathInternalCh()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_dma.h574 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
593 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
612 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_IsEnabledChannel()
647 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_ConfigTransfer()
673 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_SetDataTransferDirection()
697 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetDataTransferDirection()
722 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, in LL_DMA_SetMode()
744 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMode()
767 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, in LL_DMA_SetPeriphIncMode()
789 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
Dstm32l4xx_ll_dmamux.h526 …l_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_DMAREQ… in LL_DMAMUX_SetRequestID()
648 …ypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ… in LL_DMAMUX_GetRequestID()
675 …ypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_NBREQ,… in LL_DMAMUX_SetSyncRequestNb()
701 …ypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_NBREQ)… in LL_DMAMUX_GetSyncRequestNb()
732 …l_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SPOL, … in LL_DMAMUX_SetSyncPolarity()
762 …l_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SPOL)); in LL_DMAMUX_GetSyncPolarity()
788 …nel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_EnableEventGeneration()
814 …nel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE); in LL_DMAMUX_DisableEventGeneration()
840 …ypeDef *)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE) =… in LL_DMAMUX_IsEnabledEventGeneration()
866 …nnel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE); in LL_DMAMUX_EnableSync()
[all …]
Dstm32l4xx_hal_dma.h473 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
480 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
606 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRU…
618 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERR…
630 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTE…
Dstm32l4xx_ll_adc.h2459 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); in LL_ADC_SetCommonClock()
2487 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); in LL_ADC_GetCommonClock()
2521 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); in LL_ADC_SetCommonPathInternalCh()
2543 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); in LL_ADC_GetCommonPathInternalCh()
5611 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode); in LL_ADC_SetMultimode()
5635 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); in LL_ADC_GetMultimode()
5686 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer); in LL_ADC_SetMultiDMATransfer()
5732 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG)); in LL_ADC_GetMultiDMATransfer()
5772 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); in LL_ADC_SetMultiTwoSamplingDelay()
5800 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); in LL_ADC_GetMultiTwoSamplingDelay()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_dma.h509 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_EnableChannel()
528 …annel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); in LL_DMA_DisableChannel()
547 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_IsEnabledChannel()
582 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_ConfigTransfer()
608 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_SetDataTransferDirection()
632 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetDataTransferDirection()
657 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, in LL_DMA_SetMode()
679 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMode()
702 …nnel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, in LL_DMA_SetPeriphIncMode()
724 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphIncMode()
[all …]
Dstm32l1xx_ll_i2c.h638 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle); in LL_I2C_SetDutyCycle()
651 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY)); in LL_I2C_GetDutyCycle()
665 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode); in LL_I2C_SetClockSpeedMode()
678 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS)); in LL_I2C_GetClockSpeedMode()
715 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod); in LL_I2C_SetClockPeriod()
726 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR)); in LL_I2C_GetClockPeriod()
776 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig); in LL_I2C_ConfigSpeed()
Dstm32l1xx_hal_dma.h328 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
335 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
548 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRU…
560 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERR…
572 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTE…
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_dma.c209 tmp = hdma->Instance->CCR; in HAL_DMA_Init()
223 hdma->Instance->CCR = tmp; in HAL_DMA_Init()
239 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); in HAL_DMA_Init()
341 hdma->Instance->CCR = 0; in HAL_DMA_DeInit()
371 hdma->DMAmuxChannel->CCR = 0; in HAL_DMA_DeInit()
528 if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) in HAL_DMA_Start_IT()
531 hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; in HAL_DMA_Start_IT()
578 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMA_Abort()
639 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMA_Abort_IT()
699 if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC)) in HAL_DMA_PollForTransfer()
[all …]
Dstm32l4xx_hal_dac_ex.c403 …MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel… in HAL_DACEx_SelfCalibrate()
425 …MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel… in HAL_DACEx_SelfCalibrate()
436 …MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel… in HAL_DACEx_SelfCalibrate()
488 …MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Chan… in HAL_DACEx_SetUserTrimming()
517 return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL)); in HAL_DACEx_GetTrimOffset()
Dstm32l4xx_hal_qspi.c679 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_IRQHandler()
1027 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit()
1115 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive()
1204 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_IT()
1265 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_IT()
1379 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_DMA()
1395 MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Transmit_DMA()
1537 MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Receive_DMA()
1543 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_DMA()
2342 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_Abort()
[all …]
Dstm32l4xx_hal_dma_ex.c133 MODIFY_REG( hdma->DMAmuxChannel->CCR, \ in HAL_DMAEx_ConfigMuxSync()
261 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMAEx_MUX_IRQHandler()
Dstm32l4xx_ll_dma.c217 CLEAR_BIT(tmp->CCR, DMA_CCR_EN); in LL_DMA_DeInit()
220 LL_DMA_WriteReg(tmp, CCR, 0U); in LL_DMA_DeInit()
Dstm32l4xx_hal_ospi.c1050 WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 | in HAL_OSPI_HyperbusCmd()
1191 if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) in HAL_OSPI_Receive()
1340 if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) in HAL_OSPI_Receive_IT()
1454 MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); in HAL_OSPI_Transmit_DMA()
1579 MODIFY_REG(hospi->hdma->Instance->CCR, DMA_CCR_DIR, hospi->hdma->Init.Direction); in HAL_OSPI_Receive_DMA()
1594 if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) in HAL_OSPI_Receive_DMA()
1673 if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) in HAL_OSPI_AutoPolling()
1761 if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) in HAL_OSPI_AutoPolling_IT()
2772 ccr_reg = &(hospi->Instance->CCR); in OSPI_ConfigCmd()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_dma.c205 tmp = hdma->Instance->CCR; in HAL_DMA_Init()
219 hdma->Instance->CCR = tmp; in HAL_DMA_Init()
281 hdma->Instance->CCR = 0; in HAL_DMA_DeInit()
523 if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) in HAL_DMA_PollForTransfer()
613 uint32_t source_it = hdma->Instance->CCR; in HAL_DMA_IRQHandler()
619 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) in HAL_DMA_IRQHandler()
640 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) in HAL_DMA_IRQHandler()
Dstm32l1xx_ll_dma.c205 CLEAR_BIT(tmp->CCR, DMA_CCR_EN); in LL_DMA_DeInit()
208 LL_DMA_WriteReg(tmp, CCR, 0U); in LL_DMA_DeInit()
Dstm32l1xx_hal_adc.c460 MODIFY_REG(ADC->CCR , in HAL_ADC_Init()
720 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE); in HAL_ADC_DeInit()
1735 if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET) in HAL_ADC_ConfigChannel()
1737 SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); in HAL_ADC_ConfigChannel()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/saml21/hri/
Dhri_systemcontrol_l21.h1122 ((Systemcontrol *)hw)->CCR.reg |= SystemControl_CCR_UNALIGN_TRP; in hri_systemcontrol_set_CCR_UNALIGN_TRP_bit()
1129 tmp = ((Systemcontrol *)hw)->CCR.reg; in hri_systemcontrol_get_CCR_UNALIGN_TRP_bit()
1138 tmp = ((Systemcontrol *)hw)->CCR.reg; in hri_systemcontrol_write_CCR_UNALIGN_TRP_bit()
1141 ((Systemcontrol *)hw)->CCR.reg = tmp; in hri_systemcontrol_write_CCR_UNALIGN_TRP_bit()
1148 ((Systemcontrol *)hw)->CCR.reg &= ~SystemControl_CCR_UNALIGN_TRP; in hri_systemcontrol_clear_CCR_UNALIGN_TRP_bit()
1155 ((Systemcontrol *)hw)->CCR.reg ^= SystemControl_CCR_UNALIGN_TRP; in hri_systemcontrol_toggle_CCR_UNALIGN_TRP_bit()
1162 ((Systemcontrol *)hw)->CCR.reg |= SystemControl_CCR_STKALIGN; in hri_systemcontrol_set_CCR_STKALIGN_bit()
1169 tmp = ((Systemcontrol *)hw)->CCR.reg; in hri_systemcontrol_get_CCR_STKALIGN_bit()
1178 tmp = ((Systemcontrol *)hw)->CCR.reg; in hri_systemcontrol_write_CCR_STKALIGN_bit()
1181 ((Systemcontrol *)hw)->CCR.reg = tmp; in hri_systemcontrol_write_CCR_STKALIGN_bit()
[all …]
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_hal_dma.c170 tmp = hdma->Instance->CCR; in HAL_DMA_Init()
184 hdma->Instance->CCR = tmp; in HAL_DMA_Init()
275 hdma->Instance->CCR = 0U; in HAL_DMA_DeInit()
455 while((hdma->Instance->CCR & DMA_CCR_EN) != 0U) in HAL_DMA_Abort()
658 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) in HAL_DMA_IRQHandler()
682 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) in HAL_DMA_IRQHandler()
Dstm32l0xx_hal_adc.c450 ADC->CCR &= (uint32_t)~ADC_CCR_LFMEN; in HAL_ADC_Init()
451 ADC->CCR |=__HAL_ADC_CCR_LOWFREQUENCY(hadc->Init.LowPowerFrequencyMode); in HAL_ADC_Init()
1674 ADC->CCR |= ADC_CCR_TSEN; in HAL_ADC_ConfigChannel()
1683 ADC->CCR |= ADC_CCR_VREFEN; in HAL_ADC_ConfigChannel()
1690 ADC->CCR |= ADC_CCR_VLCDEN; in HAL_ADC_ConfigChannel()
1705 ADC->CCR &= ~ADC_CCR_TSEN; in HAL_ADC_ConfigChannel()
1711 ADC->CCR &= ~ADC_CCR_VREFEN; in HAL_ADC_ConfigChannel()
1718 ADC->CCR &= ~ADC_CCR_VLCDEN; in HAL_ADC_ConfigChannel()
Dstm32l0xx_ll_dma.c204 CLEAR_BIT(tmp->CCR, DMA_CCR_EN); in LL_DMA_DeInit()
207 LL_DMA_WriteReg(tmp, CCR, 0U); in LL_DMA_DeInit()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/saml21/cmsis/
Dcore_cm7.h417 …__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register … member
1889 SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache in SCB_EnableICache()
1905 SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache in SCB_DisableICache()
1956 SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache in SCB_EnableDCache()
1982 SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache in SCB_DisableDCache()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/cmsis/
Dcore_cm7.h507 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
2079 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
2095 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
2149 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
2173 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()

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