Searched refs:__O (Results 1 – 23 of 23) sorted by relevance
263 #define __O volatile /*!< Defines 'write only' permissions */ macro392 …__O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…438 …__O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Regi…444 …__O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU …446 …__O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU …447 …__O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC …448 …__O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way …449 …__O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU …450 …__O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC …451 …__O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way …[all …]
202 #define __O volatile /*!< Defines 'write only' permissions */ macro330 …__O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…662 __O union664 …__O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit …665 …__O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit …666 …__O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit …675 …__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register …679 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register …1155 …__O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
202 #define __O volatile /*!< Defines 'write only' permissions */ macro330 …__O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…642 __O union644 …__O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit …645 …__O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit …646 …__O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit …655 …__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register …659 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register …1135 …__O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
248 #define __O volatile /*!< Defines 'write only' permissions */ macro377 …__O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…702 __O union704 …__O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit …705 …__O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit …706 …__O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit …715 …__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register …719 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register …1301 …__O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
197 #define __O volatile /*!< Defines 'write only' permissions */ macro
207 #define __O volatile /*!< Defines 'write only' permissions */ macro
202 #define __O volatile /*!< Defines 'write only' permissions */ macro
307 __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */309 __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */312 …__O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vecto…
448 __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */449 __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */
293 __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */
1662 …__O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT E…1663 …__O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT E…1678 …__O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point…1679 …__O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point…
388 …__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration …
863 …__O TAL_HALT_Type HALT; /**< \brief Offset: 0x0C ( /W 8) Debug Halt Request */864 …__O TAL_RESTART_Type RESTART; /**< \brief Offset: 0x0D ( /W 8) Debug Restart Reques…
579 __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
594 __O EVSYS_SWEVT_Type SWEVT; /**< \brief Offset: 0x1C ( /W 32) Software Event */
565 __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
212 #define __O volatile /*!< Defines 'write only' permissions */ macro
222 #define __O volatile /*!< Defines 'write only' permissions */ macro
217 #define __O volatile /*!< Defines 'write only' permissions */ macro
270 #define __O volatile /*!< Defines 'write only' permissions */ macro
285 #define __O volatile /*!< Defines 'write only' permissions */ macro
